Method for fabricating dual gate dielectric layers

Details Method for fabricating dual gate dielectric layers Method for fabricating dual gate dielectric layers

1999-04-26

2001-07-24

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

C438S239000

Reexamination Certificate

active

06265325

ABSTRACT:

TECHNICAL FIELD
The invention relates generally to the fabrication of semiconductor devices, and more particularly to the fabrication of two different gate dielectric layers on the same substrate.
BACKGROUND ART
Many integrated circuits that perform multiple functions require transistors having different operating characteristics on the same chip. Specifically, transistors having different gate dielectric (oxide) thicknesses are needed on the same chip to accommodate different voltage requirements.
One prior art technique for fabricating an integrated circuit having two different gate dielectric thicknesses that correspond to two different device areas involves a single photolithographic process. According to the technique, a first gate dielectric is formed on a substrate over two device areas, with the two device areas being electrically separated by field oxide. A photoresist mask is used to protect the gate dielectric over the first device area, while the gate dielectric over the second device area is removed using known etching techniques. The photoresist mask is then removed from the first gate dielectric and a second gate dielectric is formed. In the process of forming the second gate dielectric on the second device area, the thickness of the first gate dielectric is increased by approximately the same thickness as the second gate dielectric. The result of the process is a first gate dielectric having a first thickness and a second gate dielectric having a second thickness. Although the fabrication process is able to generate two different gate dielectrics with a single photolithographic step, the process requires direct contact between the first gate dielectric and the photoresist. Photoresist is known to be a significant source of contamination to gate dielectrics and, therefore, it is preferable to avoid direct contact between gate dielectrics and photoresist.
A fabrication technique that does not involve direct contact between gate dielectrics and photoresist is disclosed in U.S. Pat. No. 5,668,035, entitled “Method for Fabricating a Dual-Gate Dielectric Module for Memory with Embedded Logic Technology,” issued to Fang et al. (hereinafter Fang). In accordance with the Fang fabrication technique, a first gate oxide (dielectric) layer is formed on two device areas of a substrate. A first polysilicon layer is deposited onto the first gate oxide layer that exists over the first and second device areas. The first polysilicon layer is then removed over the first device area utilizing a first photolithographic step. The first gate oxide layer is also removed over the first device area and a new, thinner, gate oxide layer is deposited over the first device area. A second polysilicon layer is deposited over both the first and second device areas. Portions of the second polysilicon layer are removed utilizing a second photolithographic step in order to even out the thicknesses of the first and second polysilicon layers that exist above the two gate oxide layers. Further known processing techniques are utilized to complete the desired devices. Although the Fang method avoids applying photoresist directly onto a gate oxide layer, the Fang method requires two photolithographic steps to create the dual gate dielectric layers. Photolithographic steps are a significant cost in the fabrication of semiconductor devices and, therefore, it is preferable to minimize the number of photolithographic steps that are required.
As a result of the stated shortcomings of the prior art techniques for fabricating dual gate dielectric layers, what is needed is a method for fabricating dual gate dielectric layers that avoids direct contact between gate oxide layers and photoresist, while minimizing the number of photolithographic processing steps that are required.
SUMMARY OF THE INVENTION
A method for fabricating dual gate dielectric layers on a semiconductor substrate involves utilizing a single photolithographic step to form layer stacks having two different gate dielectric layers and associated polysilicon layers, and then utilizing a physical planarization process to remove excess polysilicon and silicon oxide. The formation of the two gate dielectric layers includes associated polysilicon layers to ensure that the gate dielectric layers are never in direct contact with photoresist. Additionally, the method utilizes a physical planarization process to remove excess polysilicon and silicon oxide, where known prior art techniques utilize a second photolithographic step and chemical processing to remove excess polysilicon and silicon oxide. The physical planarization process is preferably a chemical mechanical polishing (CMP) process that removes excess polysilicon and silicon oxide from the layer stacks through abrasion.
A preferred method for fabricating dual gate dielectric layers is described for two gate dielectric layers that are formed over distinct first and second device areas of a silicon substrate. Initially, areas of field oxide are formed around the first and second device areas to electrically isolate the two device areas from each other. The field oxide areas are preferably grown using known oxidation techniques.
A first gate dielectric layer is then formed on the first and second device areas utilizing known thermal oxidation techniques. A first polysilicon layer is deposited onto the first gate dielectric layer and onto the areas of field oxide. The first polysilicon layer is preferably deposited utilizing low pressure chemical vapor deposition techniques.
After the first polysilicon layer is deposited, a photolithographic step is employed to form a pattern of photoresist on the first polysilicon layer. In the preferred method, photoresist covers the polysilicon layer over the first device area and peripheral areas, but not over the second device area.
The first polysilicon layer is then removed in areas where the first polysilicon layer is not protected by photoresist, thereby exposing the gate dielectric layer that is over the second device area. The first polysilicon layer is preferably removed utilizing a conventional etching process, such as an isotropic plasma etching.
The first gate dielectric layer over the second device area is then removed by means of a known etching technique, such as wet etching with a solution of hydrofluoric acid and deionized water. A second gate dielectric layer is formed on the exposed second device area and concurrently, a silicon oxide layer is formed on the first polysilicon layer that surrounds the second device area. In the preferred method, the second gate dielectric layer occupies a smaller surface area than the first gate dielectric layer.
A second polysilicon layer is blanket deposited onto the second gate dielectric layer and onto the silicon dioxide layer of the second device area. The second polysilicon layer is preferably deposited utilizing low pressure chemical vapor deposition techniques.
Portions of the second polysilicon layer are then removed utilizing a physical planarization technique. The preferred planarization technique is a chemical mechanical polishing technique that involves contacting the second polysilicon layer with rotating polishing elements and a liquid polishing agent. In one embodiment of the method, only the portion of the second polysilicon layer in the areas surrounding the second device is removed by chemical mechanical polishing. In a preferred embodiment of the method, portions of the dielectric layer in the areas surrounding the second device area are also removed in the chemical mechanical polishing process. In addition, it is preferred that portions of the first polysilicon layer are removed during chemical mechanical polishing in order to create a common plane between the first polysilicon layer and the second polysilicon layer. This improves the results of subsequent photolithographic steps.
In an enhancement to the preferred method, dummy polysilicon features are preserved over large areas of the field oxide in order to facilitate the planarization process. Because planarization is a physical process

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