Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-02-10
2003-12-30
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000
Reexamination Certificate
active
06670227
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to integrated circuit fabrication, and more particularly, to a method for fabricating devices in core and periphery regions of a semiconductor substrate having narrow spacers while using disposable wide spacers for forming the drain and source of the device in the periphery region.
BACKGROUND OF THE INVENTION
FIG. 1
shows a cross-sectional view of a first integrated circuit device which is a flash memory cell
102
formed within a core region
104
of a semiconductor substrate
106
and of a second integrated circuit device which is a high voltage field effect transistor
108
formed within a periphery region
110
of the semiconductor substrate
106
. For example, the flash memory cell
102
may be part of an array of flash memory cells formed within a core region area of the semiconductor substrate
106
, and the high voltage field effect transistor
108
may be part of an integrated circuit formed within a periphery region area of the semiconductor substrate
106
for supporting operation of the array of flash memory cells. Such flash memory devices are known to one of ordinary skill in the art of memory device fabrication.
For fabricating the flash memory cell
102
, a flash memory cell gate stack
112
is formed on an active area of the semiconductor substrate
106
within the core region
104
. The active area of the semiconductor substrate
106
within the core region
104
is defined by the surrounding shallow trench isolation structures
122
and
124
. The flash memory cell gate stack
112
includes a tunnel dielectric
114
, a floating gate
116
, a control dielectric
118
, and a control gate
120
. Such a gate stack
112
for a flash memory cell is known to one of ordinary skill in the art of memory device fabrication.
In addition, a source bit line junction
134
and a drain bit line junction
136
are formed within the core region
104
of the semiconductor substrate
106
to the sides of the flash memory cell gate stack
112
. The source and drain bit line junctions
134
and
136
are typically formed from implantation of a dopant into exposed portions of the core region
104
of the semiconductor substrate
106
after formation of the flash memory cell gate stack
112
. An implantation mask would be formed over the periphery region
110
during such an implantation process for forming the source and drain bit line junctions
134
and
136
. Such processes for forming the source and drain bit line junctions
134
and
136
of the flash memory cell
102
are known to one of ordinary skill in the art of memory device fabrication.
For fabricating the high voltage field effect transistor
108
, a transistor gate stack
128
is formed on an active area of the semiconductor substrate
106
within the periphery region
110
. The active area of the semiconductor substrate
106
within the periphery region
110
is defined by the surrounding shallow trench isolation structures
124
and
126
. The transistor gate stack
128
includes a gate dielectric
130
and a transistor gate
132
. Such a gate stack
128
for a high voltage field effect transistor is known to one of ordinary skill in the art of memory device fabrication. The thickness of the gate dielectric
130
is typically larger such that the field effect transistor
108
has a larger threshold voltage and a higher gate break-down voltage for the high voltage field effect transistor
108
that operates with higher bias voltages such as
9
Volts for example.
Referring to
FIGS. 1 and 2
, a dopant is implanted into exposed regions of the periphery region
110
of the semiconductor substrate
106
for forming LDD (lightly doped drain) regions
138
and
140
to the sides of the transistor gate stack
128
. An implantation mask
137
is formed over the core region
104
of the semiconductor substrate
106
such that the LDD regions
138
and
140
are formed for the high voltage field effect transistor
108
. The dopant may be an N-type dopant such as arsenic or may be P-type dopant such as boron. Implantation processes for formation of such LDD regions
138
and
140
are known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to
FIGS. 2 and 3
, after formation of the LDD regions
138
and
140
for the high voltage field effect transistor
108
, first spacers
142
are formed at the sidewalls of the flash memory cell gate stack
112
, and second spacers
144
are formed at the sidewalls of the transistor gate stack
128
. The first and second spacers
142
and
144
are comprised of a dielectric material such as silicon dioxide (SiO
2
) for example, and processes for formation of such spacers
142
and
144
are known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to
FIGS. 3 and 4
, after formation of the first and second spacers
142
and
144
, a dopant is implanted to form a drain junction
150
and a source junction
152
of the high voltage field effect transistor
108
. An implantation mask
153
is formed over the core region
104
of the semiconductor substrate
106
such that the drain and source junctions
150
and
152
are formed for the high voltage field effect transistor
108
. The dopant may be an N-type dopant such as arsenic or may be P-type dopant such as boron. Implantation processes for formation of such drain and source junctions
150
and
152
are known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to
FIGS. 4 and 5
, a drain bit line silicide
156
is formed with the drain bit line junction
136
for providing contact to the drain bit line of the flash memory cell
102
. In addition, a drain silicide
158
is formed with the drain junction
150
for providing contact to the drain of the high voltage field effect transistor, and a source silicide
160
is formed with the source junction
152
for providing contact to the source of the high voltage field effect transistor
108
. Furthermore, a gate silicide
164
is formed with the transistor gate
132
for providing contact to the gate of the high voltage field effect transistor
108
. Processes for forming such suicides
156
,
158
,
160
, and
164
are known to one of ordinary skill in the art of integrated circuit fabrication.
A silicide is not shown to be formed with the source bit line junction
134
and the control gate
120
for the flash memory cell
102
in
FIG. 5
because the source bit line junctions for the array of flash memory cells are coupled together and because the control gates for a row of flash memory cells are coupled together. Then, contacts are made to the coupled source bit line junctions and the coupled control gates outside of the active device area for the flash memory cell
102
, as known to one of ordinary skill in the art of flash memory devices.
Referring to
FIGS. 5 and 6
, via structures
174
,
176
,
178
, and
180
are formed through an inter-level dielectric layer
182
to the silicides
156
,
158
,
164
, and
160
, respectively, for providing connection between the flash memory cell
102
or the high voltage field effect transistor
108
to interconnect structures
188
,
190
,
192
, and
194
, respectively. Processes for formation of such via structures and such interconnect structures are known to one of ordinary skill in the art of integrated circuit fabrication.
Referring back to
FIG. 5
, the spacers
142
and
144
are formed to have a spacer width
166
. Given a predetermined width of the gate stacks
112
and
128
and given the active device area for fabricating the flash memory cell
102
and the field effect transistor
108
, the width
166
of the spacers
142
and
144
limits the width
168
of the drain and source silicides
156
,
158
, and
160
. If the width
166
of the spacers
142
and
144
is wider, then less space is available for forming the drain and source suicides
156
,
158
, and
160
.
Referring to
FIG. 7
, during formation of the via structure
174
, the via structure
174
may be misaligned to be shifted
Ho Kei-Leong
Thio Hsiao-Han
LandOfFree
Method for fabricating devices in core and periphery... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating devices in core and periphery..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating devices in core and periphery... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3139462