Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2009-11-23
2011-10-04
Hoang, Quoc (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C257SE21658
Reexamination Certificate
active
08030158
ABSTRACT:
Disclosed is a method for fabricating a contact in a semiconductor device, including: obtaining a pattern layout including bit lines arranged across a cell matrix region of a semiconductor substrate, cell storage node contacts arranged to pass through a portion of a first interlayer insulation layer between the bit lines, and dummy storage node contacts additionally arranged in an end of the arrangement of the cell storage node contacts; and forming the cell storage node contacts and the dummy storage node contacts using the pattern layout.
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patent: 2003/0168686 (2003-09-01), Hayashi et al.
patent: 2008/0305628 (2008-12-01), Hayashi et al.
patent: 2009/0181529 (2009-07-01), Kang et al.
patent: 10-2006-0022573 (2006-03-01), None
patent: 10-2009-0027469 (2009-03-01), None
Jeon Jin Hyuck
Kang Chun Soo
Hoang Quoc
Hynix Semiconductor
Marshall & Gerstein & Borun LLP
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