Method for fabricating contacts in a semiconductor device

Details Method for fabricating contacts in a semiconductor device Method for fabricating contacts in a semiconductor device

1999-07-09

2001-06-26

Le, Hoanganh (Department: 2821)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S694000

Reexamination Certificate

active

06251790

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a contact structure and a method for fabricating thereof, and more particularly relates to a contact structure including a recessed contact plug in a contact hole and a sidewall spacer formed on both sidewalls of the remainder of the contact hole and a method for fabricating thereof.
BACKGROUND OF THE INVENTION
A connection between a conductive region of an impurity diffused layer in a semiconductor substrate or a lower level wiring and an upper level wiring layer through a contact hole formed in an interlayer insulating film is one of the more important fabrication techniques in a semiconductor device. As the degree of the integration density of integrated circuit device increases, contact openings formed in the insulating layer are required to have a small opening size to ensure a high density device. In order to increase alignment margins between contact openings and overlying conductors, it is necessary that the critical dimension of the contact openings be reduced.
A conventional method for forming a contact in a semiconductor device is schematically illustrated in
FIGS. 1A and 1B
. Referring to
FIG. 1A
, an insulating layer
2
is formed on a semiconductor substrate (not shown). The insulating layer
2
is etched to form contact holes
4
that expose conductive regions of a semiconductor substrate. A conductive material
6
such as doped polysilicon as for a storage node is deposited on the resulting structure. Through conventional photolithographic process, the polysilicon layer
6
between the contact holes
4
is etched to form storage nodes
6
a
that are electrically connected to conductive region of the semiconductor substrate as shown in FIG.
1
B. However, there are some problems with this method. If misalignment occurs during the photolithographic process, the polysilicon may be over-etched at the neck part (see reference numeral
7
) of the storage node
6
b
and in severe case, the storage node
6
b
may fall down.
Another conventional contact in a semiconductor device is schematically shown in
FIGS. 3 and 4
.
FIG. 3
schematically shows top plan views of bit line patterns and
FIG. 4
is a cross-sectional view of bit line pattern and contact plug taken along line A-A′ of FIG.
3
. In
FIG. 3
, in order to increase alignment margins between bit lines
16
a
and
16
c
and bit line contacts (see reference number
14
of FIG.
4
), portions of the bit line patterns are formed to have enlarged portions (see reference number
17
) at regions where contact is to be made. Such enlarged portions
17
may be a serious obstacle to smaller feature size. Also an electrical bridge between adjacent bit line patterns may occur.
SUMMARY OF THE INVENTION
The present invention was made in view of the above problems associated with the prior art, and it is therefore an object of the invention to provide a method for forming contacts in a semiconductor device that increase alignment margins between contact plugs and overlying conductors by reducing critical dimension of the contact holes.
It is another object of the invention to provide a method for forming contacts in a semiconductor device that can prevent storage nodes from falling down due to overetching in case of misalignment.
To achieve this and other advantages and in accordance with the purpose of the present invention, recessed contact plug is formed in a contact hole formed in an insulating layer. A sidewall spacer is further formed in remainder of the contact hole to reduce critical dimension of the contact size. Accordingly, alignment margins to laterformed overlying conductors can be increased. The recessed contact plug decreases the height of the contact hole, i.e., reduces aspect ratio thereof. Accordingly, the sidewall spacer can be formed to have a good deposition profile. Overlying conductors such as storage nodes can be easily formed to be electrically connected to the plugs without defects even in the presence of misalignment.
More specifically, an insulating layer comprising an oxide is formed on a semiconductor substrate. The semiconductor substrate has a conductor region, e.g., impurity diffusion region. A selected portion of the insulating layer is etched to form a contact hole through photolithographic process. The contact hole exposes the conductor region of the semiconductor substrate. A conductive material is deposited in the contact hole and on the insulating layer and then etched back to form a contact plug that is recessed at predetermined depth from a top surface of the insulating layer in the contact hole. Accordingly, the remainder of contact hole has a low aspect ratio thereof as compared to the initial contact hole. The conductive material deposited in the contact hole may include silicon, tungsten, aluminum, titanium, titanium nitride, tungsten nitride, copper, platinum, Au (gold) and Ag (silver).
A sidewall spacer is then formed on both sidewalls of the remainder of contact hole. The spacer can have a good sidewall profile due to reduced height of the contact hole. The sidewall spacer is provided to reduce critical dimension of the contact hole, which allows the formation of small contact hole exceeding the photolithographic resolution and allows increased alignment margins with respect to later-formed conductor pattern. The sidewall spacer is made of a material that has an etching selectivity with respect to the later-formed upper conductor. As an example, material such as tungsten, titanium, silicon and compounds such as silicon oxide (Si—O), silicon oxynitride (Si—O—N), silicon nitride (Si—N), aluminum oxide (Al—O), aluminum nitride (Al—N), boron nitride (B—N), titanium nitride (Ti—N), tungsten silicide (W—Si) and tungsten nitride (W—N).
After that, a conductive material is deposited in the remainder of the contact hole and on the insulating layer and patterned to form the upper conductor. For example, the upper conductor can be a storage node. In this case, polysilicon layer is deposited in the remainder of contact hole and on the insulating layer to a thickness that defines the height of the storage node.
Also, the upper conductor can be a bit line. In this case, there is no need for bit line tap in order to increase alignment margins. Accordingly, spaces between adjacent bit lines can be reduced without electrical bridge therebetween.
Also, after forming the recessed contact plug and sidewall spacer, the remainder of contact hole is deposited with a conductive material and then planarized down to the top surface of the insulating layer. After that, another conductive layer is deposited on the insulating layer and patterned into desired conductor pattern.


REFERENCES:
patent: 5534462 (1996-07-01), Fiordalice et al.
patent: 6001660 (1999-12-01), Park et al.
patent: 6027966 (2000-02-01), Saenger et al.

Affiliated with

Also associated with

Rating

Method for fabricating contacts in a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating contacts in a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating contacts in a semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2546120