Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-16
2001-10-02
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S399000, C438S481000, C438S618000, C438S631000, C438S637000
Reexamination Certificate
active
06297091
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly, to a method for fabricating contact pads for semiconductor devices, which permits an adequate fabrication allowance and simplifies the fabrication process of the contact pad.
2. Background of the Related Art
As high density semiconductor device packing improves, there has been a great deal of research into forming sub-micron patterns required for high density semiconductor device packing. Particularly, for formation of a contact pad mostly used for securing an alignment allowance in a cell transistor including both a bitline contact for electrically connecting a bitline and a drain, and a storage node contact for connecting a storage node and a source, through a sub-micron pattern ranging down to 0.1 &mgr;m, there have been difficulties due to limitations of photolithography.
Fabrication of a related art contact pad for a semiconductor device will be explained with reference to the attached drawings.
FIG. 1
illustrates a layout of a related art semiconductor device, and
FIGS. 2A-2D
illustrate cross-sections along A-A′ in
FIG. 1
showing the steps of a related art method for fabricating a contact pad.
Referring to
FIG. 1
, the related art method for fabricating a contact pad employs an anisotropic epitaxial growth, wherein active regions
12
is defined by a field oxide film formed in a device isolation region
13
, and wordlines
11
, disposed in a short axis direction of the active region
12
, are formed. Contact pads
14
are formed on active regions on both sides centered around the wordline. A bitline contact
15
is formed in the contact pad
14
on one side of the wordline. A storage node contact
16
is formed in the contact pad
14
on the other side of the wordline
11
.
A related art process for fabricating the contact pad for a semiconductor memory will be explained with reference to
FIGS. 2A-2D
, showing a cross-section along line A-A′.
Referring to
FIG. 2A
, a field oxide film
2
is formed on a device isolation region in a semiconductor substrate
1
to define an active region. A plurality of wordlines
11
, spaced at fixed intervals, are formed, and a sidewall insulating layer
3
covering sides and a top of each wordline
11
is formed. Ions are lightly implanted before formation of the sidewall insulating layer
3
, and ions are heavily implanted after formation of the sidewall insulating layer
3
, to form source/drain regions (not shown) in a surface of the semiconductor substrate
1
on both sides of the wordline
11
.
Then, as shown in
FIG. 2B
, an anisotropic epitaxial growth is selectively conducted to grow the semiconductor substrate
1
that is exposed on both sides of the wordline
11
, to form contact pads
14
. The anisotropic epitaxial growth prevents merging of adjacent contact pads
14
due to lateral growth of the silicon layer, which can happen if the silicon layer is grown isotropically.
As shown in
FIG. 2C
, an interlayer insulating layer
4
is formed on an entire surface, and bitline contact pads are opened selectively, to form a plug layer and a bitline
5
. Then, as shown in
FIG. 2D
, another interlayer insulating layer
6
is formed on an entire surface, including the bitline
5
, and storage node contact pads are selectively opened, to form a plug layer and a storage node
7
.
Alternatively, polysilicon may be put in spaces between wordlines before formation of the plug layer, and the polysilicon is selectively removed, leaving only the contact pad regions as they. However, this fabrication method is complicated and inefficient.
The related art method for fabricating a contact pad has the following problems.
The high degree of vacuum required, in a range of 1.0E9-1.0E10 Torr, for the anisotropic epitaxial growth is not favorable in view of equipment and process management compared to a general epitaxial growth.
In a COB structured DRAM in which a bitline passes not right over an active region of a cell, but between active regions, the contact pad formed on the active region should be extended to a position where the bitline is formed, for bringing the bitline into contact with the active region. Accordingly, the anisotropic epitaxial growth should be conducted considering the extension of the contact pad, which complicates the fabrication process and the device structure.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for fabricating a contact pad for a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for fabricating a contact pad for a semiconductor device, which permits an adequate process allowance and simplifies a fabrication process in formation of the contact pad.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method for fabricating a contact pad for a semiconductor device includes the steps of forming device isolation layers in a semiconductor substrate to define active regions, forming a plurality of wordlines crossing the active regions, forming an insulating layer on an entire surface, and selectively removing the insulating layer on storage node contact regions, a bitline contact region, and the device isolation layer in contact with the bitline contact region, to form an epitaxial growth blocking layer, and conducting an epitaxial growth using the epitaxial growth blocking layer as a mask, to form a storage node contact pad as well as a bitline contact pad by causing an epitaxial layer grown in the bitline contact region to extend laterally toward the device isolation layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5296400 (1994-03-01), Park et al.
patent: 5395784 (1995-03-01), Lu et al.
Kim Bong Soo
Kim Sang Hyun
Roh Jae Sung
Bowers Charles
Hyundai Micro Electronics Co., Ltd.
Morgan & Lewis & Bockius, LLP
Sarkar Asok Kumar
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