Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-28
2003-05-20
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S266000, C438S280000
Reexamination Certificate
active
06566197
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a flash memory device, and more particularly, to a method for fabricating a connection structure to electrically connect elements of a flash memory device.
2. Description of the Background Art
A flash memory, being a non-volatile memory device, can be composed of highly integrated components that allow repetitive data storage by electrically re-writing thereto. As such, a flash memory can be used instead of magnetic memory devices, such as a hard disk for various storage device applications.
In order to further increase the integration of a cell array in the flash memory, several methods have been employed, whereby various bit lines are arranged to be commonly used by a plurality of components. The so-called “virtual ground method” employs a drain line and a source line that are alternately used. The so-called “common bit line common ground method” employs a single source line formed between two drain lines.
FIG. 1
depicts a connection structure between segment transistors and an array of memory cells in a flash memory device employing the common bit line common ground method in accordance with the conventional art. In FIG.
1
, the cell array includes at least a first memory cell block B
1
and a second memory cell block B
2
, both having the same structure and connected together symmetrically. It can be understood that additional memory cell blocks having identical configurations may be further connected to achieve the overall cell array configuration. Only two memory cell blocks are depicted for the sake of brevity in explaining the features of a conventional memory cell array.
In the first memory cell block B
1
, the gate electrodes ‘G’ of each transistor in a memory cell ‘M’ within the same array row are connected to a common cell word line
18
. The sources ‘S’ of each transistor in a memory cell ‘M’ within the same array column are connected to a common source CS. Here, two adjacent transistors in two adjacent memory cells ‘M’ of the same array row are configured such that their sources are connected together. The common source CS is also connected with a source line
19
, so that the same signal is applied to all the common sources CS in the first memory cell block B
1
. The drains ‘D’ of each transistor in a memory cell ‘M’ within the same array column are connected to a common bit line
15
a
. Each common bit line
15
a
has an end portion
17
a.
The first memory cell block B
1
further comprises a segment transistor
6
a
for each array column. Each segment transistor
6
a
has a source
10
a
connected with the end portion
17
a
of the common bit line
15
a
, a drain
12
a
connected with a data line
14
, and a gate electrode ‘G’ connected with a common cell block word line
7
a.
The second memory cell block B
2
has the same configuration as the first memory cell block B
1
, and is connected to the first memory cell block B
1
in a symmetrical and mirror-image manner. Namely, the drains of the segment transistors
6
a
at the end of the memory array columns of the first memory cell block B
1
are connected to the drains of the segment transistors
6
b
at the end of the memory array columns of the second memory cell clock B
2
via the data line
14
between the memory cell blocks B
1
, B
2
. The gate electrodes of the segment transistors
6
b
are connected to a common block word line
7
b
. The second memory block B
2
also has common bit lines
15
b
connecting the drains of the transistors in memory cells of the same array column.
A conventional method for fabricating a connection structure (indicated as region ‘A’ in
FIG. 1
) between the segment transistors
6
a
,
6
b
and the memory cell blocks B
1
, B
2
of the flash memory device in accordance with the conventional art will now be described with reference to
FIGS. 2A through 4C
.
FIGS. 2A through 2D
are cross-sectional views showing a series of processes for fabricating common bit lines and memory cells of the flash memory device in accordance with the conventional art.
FIGS. 3A through 3C
are cross-sectional views showing a series of processes for fabricating elements of the memory cells prior to forming the segment transistors of the flash memory device in accordance with the conventional art.
FIGS. 4A through 4C
are cross-sectional views showing a series of processes for fabricating a connection structure between the segment transistors and the memory cells of the flash memory device in accordance with the conventional art.
As shown in
FIG. 2A
, after a first oxide film
21
is formed on the upper surface of a substrate
20
, a first polysilicon layer
22
is formed at a portion where segment transistors are to be formed on the upper surface of the first oxide film
21
. Then, an arsenic (As) or phosphorus (P) type impurity is ion-implanted into portions of the substrate not covered by the first polysilicon layer
22
.
Thereafter, as shown in
FIG. 2B
, a diffusion process is performed at a high temperature to create an impurity diffusion layer on portions of the substrate not covered by the first polysilicon layer
22
, to thus form the common bit lines
15
a
and
15
b
also shown in
FIG. 1. A
buried oxide film
21
b
is then formed on the common bit lines
15
a
,
15
b.
Subsequently, as shown in
FIG. 2C
, a second oxide film
23
is deposited on the upper surface of the buried oxide film
21
b
by photolithography and selective etching. Here, if no misalignment or over-etching occurs during the photolithography or the etching process, the second oxide film
23
is accurately aligned on top of the buried oxide film
21
b
. However, if misalignment occurs during the photolithography or the etching process, the common bit lines
15
a
or
15
b
may be disconnected from the first oxide layer
21
. As an example,
FIG. 2D
shows the common bit line
15
b
of the second memory cell block B
2
being disconnected from the first oxide layer
21
due to misalignment during the photolithography and/or etching process.
Thereafter, as shown in
FIG. 3A
, a second polysilicon layer
24
is formed over the entire misaligned structure, and as shown in
FIG. 3B
, a second polysilicon pattern
24
a
is formed on the upper surface of the first polysilicon layer pattern
22
by performing photolithography and etching processes. Then, as shown in
FIG. 3C
, an insulation film
29
is formed on the upper surface of the second polysilicon layer pattern
24
a
and overlapping a portion of the second oxide film
23
. Subsequently, a word line
28
for each memory cell block is formed on a portion of the second oxide film
23
. This completes the conventional fabrication method of memory cell blocks, which will then be connected with segment transistors.
Thereafter, as shown in
FIG. 4A
, a photoresist
30
is formed over the word lines
28
by photolithography, while the insulation film
29
, the second polysilicon layer pattern
24
a
, the first polysilicon layer
22
, and the first oxide film
21
are all removed by etching.
However, referring back to
FIG. 2D
, because the second oxide film
23
was misaligned with the first polysilicon layer
22
, the junction portions
27
a
and
27
b
of the memory cell blocks shown in
FIG. 4A
formed upon etching the insulation film
29
, the second polysilicon layer pattern
24
a
, the first polysilicon layer
22
, and the first oxide film
21
, do not have the proper configuration. As such, the segment transistors to be subsequently formed between the memory cell blocks will not be properly connected with the common bit lines
15
a
and
15
b
of each memory cell block, as will be explained hereafter.
As shown in
FIG. 4B
, a third oxide film
33
, acting as a gate oxide film, is deposited on the upper surface of the substrate
20
between the junction portions
27
a
and
27
b
of the memory cell blocks. Gate electrodes
31
a
and
31
b
are then respectively formed on the third oxide film
33
. Then, insulating side wall spacers
32
are formed at the sides of the gate electrode
Choi Woong-Lim
Kim Yong-Hee
Kwon Wook-Hyun
Lee Sang-Bum
Na Kee-Yeol
Chaudhari Chandra
Hynix / Semiconductor Inc.
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