Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-04-25
1998-06-02
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438199, 438304, 438305, 438307, 438558, 438564, 438224, H01L 218238
Patent
active
057598851
ABSTRACT:
A method for fabricating a CMOSFET includes the steps of forming a first well of a first conduction type and a second well of a second conduction type on a substrate of the first conduction type; forming gate electrodes having sides on the first well and the second well; forming semiconductor sidewall spacers of the first conduction type at the sides of the gate electrodes; forming a semiconductor layer of the second conduction type over the first well; implanting impurity ions of the first conduction type into the second well; and annealing the semiconductor substrate to form lightly doped shallow impurity regions of the first conduction type in the first and second wells under the semiconductor sidewall spacers, and heavily doped deep impurity regions of the second conduction type in the first well, and simultaneously activating the impurity ions in the second well to formed heavily doped deep impurity regions of the first conduction type in the second well.
REFERENCES:
patent: 5506161 (1996-04-01), Orlowski et al.
Mizuki Ono et al., "Sub-50 NM Gate Length N-MOSFETS with 10 NM Phosphorous Source and Drain Junctions," IEDM 93 pp. 119-122.
M. Saito et al., "An SPDD P-MOSFET Structure Suitable for 0.1 and Sub 0.1 Micron Channel Length and its Electrical Characteristics," IEDM 92, pp. 897-900.
Mitsuhiro Togo et al., "Novel Deep Sub-Quarter Micron PMOSFETs with Ultra-shallow Junctions Utilizing Boron Diffusion from Poly-Si/Oxide (BDSOX)," 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 21-22.
LG Semicon Co. Ltd.
Niebling John
Pham Long
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