Method for fabricating CMOS transistors by implanting into polys

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438275, 438532, H01L 218238

Patent

active

060016779

ABSTRACT:
A method for fabricating MOS transistors comprises the steps of forming a polysilicon layer, having an underlying gate oxide layer on the major surface of a silicon substrate, providing a mask to cover a predetermined portion except the portion for an N-type polysilicon layer to be formed, doping the polysilicon layer uncovered by the first mask with N-type ions, providing a second mask to cover a predetermined portion except the portion for a P-type polysilicon layer to be formed, doping the polysilicon layer uncovered by the second mask with boron ions, subjecting the polysilicon layer to a patterning process to define gate electrodes of an NMOS and PMOS transistors, providing a third mask to cover a predetermined portion except the portion for an NMOS transistor to be formed, doping N-type ions into substrate portion for the NMOS transistor to be formed using the third mask and the gate electrodes as a mask to thereby form a source and a drain of the NMOS transistor, forming a silicon oxide layer over each of the gate electrodes, providing a fourth mask to cover a predetermined portion except the portion for a PMOS transistor to be formed, and doping BF.sub.2 ions into substrate portion for PMOS transistors to be formed using the fourth mask and gate electrodes overlaid by the silicon oxide layer as a mask, to thereby form source and drain regions of the PMOS transistors.

REFERENCES:
patent: 5021356 (1991-06-01), Henderson et al.
patent: 5468666 (1995-11-01), Chapman
patent: 5534448 (1996-07-01), Baldi
patent: 5744372 (1998-04-01), Bulucea
patent: 5789286 (1998-09-01), Subbanna

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