Method for fabricating CMOS transistor

Details Method for fabricating CMOS transistor Method for fabricating CMOS transistor

2002-12-31

2004-07-27

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S221000, C438S227000, C438S229000, C438S231000, C438S232000

Reexamination Certificate

active

06767780

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor memory device; and, more particularly, to a method for fabricating a CMOS transistor.
DESCRIPTION OF RELATED ARTS
A complementary metal oxide semiconductor (CMOS) transistor includes a nMOS transistor and a pMOS transistor. If the CMOS transistor is used for configuring a peripheral circuit of a memory device of 0.18 &mgr;m and below, the COMS transistor includes the 0.25 &mgr;m and larger nMOS and pMOS transistors having a gate length larger than a minimum line width. The above mentioned CMOS transistor is configured by concurrently forming a lightly doped drain (LDD) region of a surface channel nMOS transistor and a punch stop layer of a buried channel pMOS transistor. The LDD region and the punch stop layer is formed by ion implantation of an n-type dopant such as phosphorus (P) into a forming region of the nMOS transistor and a forming region of the pMOS transistor without using a mask.
FIGS. 1A
to
1
B are cross-sectional views showing a conventional process for fabricating a CMOS transistor.
Referring to
FIG. 1A
, after forming a device isolation layer for isolating each of devices in a semiconductor substrate
11
, a n-type well
13
is formed on a region of a pMOS transistor in the semiconductor substrate
11
and continuously an n-type field stop layer
14
is formed in the n-type well
13
. A p-type well
15
is formed on a nMOS transistor region in the semiconductor substrate
11
and a p-type field stop layer
16
is formed on the p-type well
15
.
After forming the p-type field stop layer
16
, a gate oxide layer
17
and a gate electrode
18
is formed on a selected region on the semiconductor substrate
11
providing the pMOS transistor and nMOS transistor. Finally, there formed an n-type punch stop layer
20
on the pMOS transistor and an n-type LDD
21
on the nMOS transistor by ion-implanting phosphorus (P) by using a blanket ion implantation and depositing a nitride layer
19
on the above entire structure.
Referring to
FIG. 1B
, after an oxide layer (not shown) is deposited on the entire structure, a spacer
22
contacting to lateral sides of the gate electrode
18
is formed by an etch-back process. At this time, the nitride layer
19
and the gate oxide layer
17
are concurrently proceeded with an etch-back process applied to an upper surface of the semiconductor substrate
11
. Reference numerals
19
A and
17
A are a remaining nitride layer and a remaining gate oxide layer, respectively.
Next, a p-type source/drain region
23
is formed by ion-implanting a p-type impurity in the pMOS transistor region, and an n-type source/drain region
24
is also formed by ion-implanting an n-type impurity on the nMOS transistor region.
In
FIGS. 1A and 1B
, when the n-type LDD doping layer
21
is formed on the nMOS transistor region, the n-type punch stop layer
20
is also formed on the pMOS transistor region.
However, in the above mentioned conventional method for fabricating the CMOS transistor, optimum characteristics of the nMOS transistor and the pMOS transistor cannot be obtained, since forming conditions for the LDD region of the nMOS transistor and the punch stop layer of the pMOS transistor are identical. As a result, one of the characteristics of the nMOS transistor and the pMOS transistor is degraded.
Furthermore, the above mentioned conventional method cannot control a short channel effect provided by each of the nMOS transistor and the pMOS transistor since a gate length of a peripheral circuit is below 0.25 &mgr;m in the memory device of above 0.15 &mgr;m.
For example, when the n-type impurity is ion-implanted for concurrently forming the LDD region and the punch stop layer, the short channel effect of the pMOS transistor is constrained according to an amount of the n-type impurity for ion-implantation, however, the short channel characteristic of the nMOS transistor is degraded. Also, when the n-type impurity is ion-implanted with a minimally increased quantity for increasing driving current of the nMOS transistor, a threshold voltage V
T
is dynamically increased and the driving current is decreased. Therefore, reducing the gate length of the MOS transistor provides a limitation in a fabricating process for the CMOS transistor.
For overcoming the above mentioned problem, another conventional CMOS transistor fabricating method is introduced by Takashi Hori et al., at “A 0.1 &mgr;m CMOS technology with tilt-implanted punch through stopper (TIPS)” IEDM, 1994 (hereinafter Takashi). The Takashi teaches a method for fabricating a CMOS transistor having a gate length around 0.1 &mgr;m. The Takashi's method individually performs ion-implantations to form the punch stop structure of a surface channel nMOS transistor and a buried channel pMOS transistor by using different masks.
FIG. 2
is a cross-sectional view of a CMOS transistor for explaining the Takashi's forming process of a CMOS transistor.
Referring to
FIG. 2
, a gate oxide layer
25
and a gate electrode
26
are formed on a semiconductor substrate
24
, and a spacer
27
is formed on both lateral sides of the gate electrode
26
. A LDD region
28
is formed at edges on both sides of the gate electrode
26
in the nMOS transistor region. An n
+
source/drain region is formed by contacting to the LDD region
28
, and the p-type punch stop layer
30
is formed on a bottom of the LDD region
28
by performing the tilted ion implantation of boron (B). In the pMOS transistor region, a p
+
source/drain region
31
is formed and an n-type punch stop layer
32
is formed on a side of the p
+
source/drain region
31
by tilted ion implanting phosphorus (P).
Atsuki Hori et al. introduces another method for fabricating a CMOS transistor in “A 0.05 &mgr;m CMOS with ultra shallow source/drain junctions fabricated by 5 KeV ion imimplantation and rapid thermal annealing” IEDM, 1994 (Hereinafter Atsuki). The Atsuki's method teaches to fabricate the nMOS transistor and the pMOS transistor in order to have a gate of 0.5 nm by using a self aligned pocket implantation (SPI) and a source/drain extension (SDE).
FIG. 3
is a cross-sectional view of a CMOS transistor for explaining the Atsuki's forming process.
Referring to
FIG. 3
, a gate oxide layer
34
and a gate electrode
35
are formed on a semiconductor substrate
33
. Also, a spacer
36
is formed on both lateral sides of the gate electrode
35
. An n
+
source/drain extension region
37
A is formed on both edges of the gate electrode
35
in the nMOS transistor region. An n
+
source/drain region
38
B is formed by contacting to the n
+
source/drain extension region
37
A. A p-type self aligned pocket layer is formed beneath of the n
+
source/drain extension region
37
A by tilted ion-implanting boron (B). An n-type self aligned pocket layer
39
A and a p
+
source/drain extension region
37
A are formed on both edges of the gate electrode
35
in the pMOS transistor region. A p
+
source/drain region
38
B is formed by contacting to the p
+
source/drain extension region
37
B and the n-type self aligned pocket layer
39
B.
As mentioned above, the Atsuki and Takasi provide methods that optimize characteristics of the nMOS transistor and the pMOS transistor. However, the methods use different masks for each of nMOS transistor region and pMOS transistor region. Additional processes such as a LDD doping process and a source/drain extension region process are performed. As a result, a complexity of a fabricating process is increased and a manufacture expense is also increased. Therefore, the above mentioned methods are incongruent for manufacturing a semiconductor memory device.
Specially, in case of the Atuski' method, arsenic (AS) is used for forming the source/drain extension region of the nMOS transistor. As a result, a problem with respect to a hot carrier is arose when the nMOS transistor is used in one of peripheral circuits, which require a higher driving voltage such as an exte

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