Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-09-19
2004-06-29
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S240000, C438S381000
Reexamination Certificate
active
06756261
ABSTRACT:
BACKGROUND
1. Technical Field
A method for fabricating a highly integrated semiconductor device is disclosed. More particularly, a method for fabricating a capacitor using a high dielectric substance as the dielectric layer is disclosed.
2. Description of the Related Art
Generally, as a semiconductor devices becomes highly integrated and miniaturized, the area occupied by the constitutional elements of these devices gets smaller. As the size of a semiconductor device shrinks, however, a minimum capacitance needs to be secured to drive the device.
When fabricating a capacitor of a 64 Mbyte or 256 Mbyte-DRAM using a conventional dielectric material such as SiO
2
or Si
3
N
4
, the area occupied by the capacitor should be more than six times as big as the cell area to secure the essential capacitance, even though the SiO
2
or Si
3
N
4
layer is made as thin as possible. As a planar capacitor cannot fulfill this condition, a method for increasing the charge storage area should be sought.
Many structures including a stack capacitor, trench capacitor, or a hemispheric polysilicon layer have been suggested to increase the charge storage area or to increase the storage node surface area of a capacitor. However, in case where the structure of a capacitor is made complicated just to increase its charge storage area, there are problems in that the production cost goes up and the efficiency declines due to complex manufacturing process.
Therefore, it is hard to apply a method of increasing the charge storage area of a capacitor by making it three-dimensional and fulfilling capacitance to a DRAM device in a 1 Gb class.
To solve these problems, studies have been done on a Ta
2
O
5
dielectric layer as a substitute for a conventional SiO
2
/Si
3
N
4
dielectric layer. However, the capacitance of a Ta
2
O
5
layer is no more than two to three times that of a SiO
2
/Si
3
N
4
dielectric layer. Accordingly, to employ a Ta
2
O
5
dielectric layer in a highly integrated DRAM, the thickness of the dielectric layer should be reduced. But, a Ta
2
O
5
dielectric layer presents has a problem because the amount of leakage current increases with its use.
For this reason, a high dielectric thin film is needed to fabricate a capacitor for 1 Gb DRAMs. When using a thin film with a high dielectric constant, it's possible to obtain adequate capacitance only by a planar capacitor, thus simplifying the manufacturing process. A BST layer, i.e., (Ba,Sr)TiO
3
, has been studied as a high dielectric material. Capacitors, with a BST layer have a capacitance dozens of times as those capacitors with SiO
2
/Si
3
N
4
layers as well as improved structure and thermal stability. Thus the excellent electric and structural properties of the capacitor with a BaTiO
3
layer which makes it an appropriate material for a memory device over a 1 Gb class.
Among other materials having high dielectric constants, the BST layer of a perovskite structure is the most appropriately applicable to a high-density and highly-integrated capacitor, which requires a high dielectric constant and small leakage current. This is because the BST layer features a high dielectric constant and superb insulation property with low dielectric dispersion and dielectric loss at a high frequency, and existing in a paraelectric at a room temperature. Furthermore, the BST layer doesn't have the problem of fatigue or degradation.
However, the dielectric constant and leakage current properties of the BST layer largely depend on its fabrication process and the kind of the electrode material, and the leakage current is far bigger than such an amorphous layer as SiO
2
/Si
3
N
4
group or Ta
2
O
5
. So the thickness of a thin film is limited to the range of 200~300 Å to make the leakage current stay within the acceptable range.
Accordingly, under active development is a method for fabricating a BST layer using a chemical vapor deposition (CVD), which can deposit a thin film on a wide area evenly with superb step coverage and improved control of the material composition as compared to a sputtering method.
Generally, a BST layer is deposited by the chemical vapor deposition (CVD) at a predetermined temperature and pressure. In the first step, the molarity of precursor, the flow rate of precursor through a liquid delivery system (LDS), the temperature of a vaporizer, the temperature of a shower head, the temperature of processes and the pressure of processes are optimized. It is commonly known to have the optimum dielectric property in a composition ratio of Ba:Sr:Ti=25:25:50 (atomic percent).
Therefore, the BST deposition by the CVD can obtain its inherent dielectric property and reduced leakage current not only by developing precursors but by optimizing the deposition condition as well so as to make the composition ratio of Ba+Sr:Ti to be close to 1:1. However, the composition ratio of a BST layer varies with temperature and thickness of deposition because the temperature of the surface of a wafer, i.e., bottom electrode, when the BST layer is initially deposited and the temperature of the surface of the wafer when a little bit of the BST layer is deposited are different.
In short, when a BST layer is deposited on the bottom electrode of the capacitor, the composition change of Ba, Sr and Ti according to the deposition temperature shows low content of Ti and high content of Sr and Ba at a low temperature of the initial step. But, at a high temperature over 450° C., the Ti content goes up to 60 atomic percent while the Sr and Ba content decreases to 10~20 atomic percent.
As the deposition is performed at a high temperature, the BST layer formed during the deposition has a high content of Ti. In the high temperature deposition condition, the BST layer with a thickness of less than approximately 200 Å shows high Ti content. That is, as the layer grows thicker the composition ratio of Ti gets lower. This is because the temperature of a wafer on which a portion of BST layer is already deposited is lower than the temperature of the wafer on which the bottom electrode is only formed. In addition, the composition of Ba, Sr and Ti changes according to pressure.
Therefore, the major factor that controls the electric property of the BST capacitor is the amount of Ti inside the BST layer. It is hard to keep the Ti amount inside the deposited whole BST layer at around 50 atomic percent, and when the Ti makes up more than 50 atomic percent, the overall electric properties of the BST capacitor, such as the thickness of valid oxide layer and the density of leakage current, are degraded.
In short, when fabricating a capacitor by depositing BST as a dielectric layer on an electrode of a noble metal, such as Pt or Ru, the Ti composition gets higher than 50 atomic percent at a high temperature during the procedure of depositing BST layer, and when the deposition temperature or process pressure is lowered to take care of the problem caused by the high temperature, the throughput of the manufacturing process is affected adversely. Also, when the Ti composition is more than 50 atomic percent, the leakage current property is degraded, which influences on the operation of a semiconductor badly.
SUMMARY OF THE INVENTION
Therefore, a method for fabricating a semiconductor device is disclosed, which does not need to lower pressure and thus does not curtail the throughput, and improves the leakage current property by controlling the composition of a dielectric layer.
In accordance with an embodiment, a method for fabricating a capacitor of a semiconductor device comprises: a) forming a bottom electrode; b) forming an STO seed layer as a first dielectric layer on the bottom electrode; c) forming a BST layer as a second dielectric layer on the STO seed layer; and d) forming a top electrode on the BST layer.
A method for forming a 5 nm thin STO(SrTiO
3
) layer is also disclosed instead of forming a BST layer, whose composition can be hardly controlled, so as to improve the leakage current property when fabricating a capacitor adopting a BST layer in a highly in
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
Nhu David
LandOfFree
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