Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-13
2001-04-17
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S255000
Reexamination Certificate
active
06218242
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to semiconductor fabrication. More particularly, the present invention relates to a method for fabricating a capacitor in a semiconductor integrated circuit.
2. Description of Related Art
A semiconductor integrated circuit usually needs a capacitor. Particularly, a memory device needs the capacitors for each memory cell to store the binary data, according to the bias level of the capacitors. For a memory device such as dynamic random access memory (DRAM), generally, an array of capacitors on the substrate are storing the binary data by charging or discharging the capacitors. One capacitor acts one bit of memory for storing the binary data “0” or “1” corresponding to the status of capacitor being “charged” or “discharged”, respectively. The action of read/write in the DRAM is done through a transfer field effect transistor (TFET), in which a source of the TFET is coupled to a bit line (BL), a drain is coupled to the capacitor and a gate is coupled to a word line (WL). The BL carries a voltage level to charge the capacitor through the TFET, where the TFET is selectively controlled by the WL to be activated or inactivated. Thus a writing action can be done. On the other hand, if one wants to read the binary data having been stored, the BL is switched to a comparator circuit, or a sense amplifier, to check the voltage status of the capacitor for the reading action. Therefore the charges stored in the capacitor is essential to a memory quality in the DRAM
The charges stored in the capacitor depends on the capacitance of the capacitor. The capacitance is determined by the storing area of the storage electrode, the isolating reliability between an upper electrode and a lower electrode of the capacitor, and dielectric constant of dielectric, which has been chosen. To be able to store more data, the density of the capacitors used in the memory device tends to increase. This results in the storage charges would be decreased. If the storage charges can stay high, the affections of noise to the sense amplifier for reading can be effectively reduced and it is not necessary to refresh the voltage level of the capacitor, frequently.
While the integration is increasing, the size of memory cell in a DRAM is reduced, accordingly. As known by one skilled in the art, the reduced size of the capacitor gives a result of lower capacitance. If the capacitance is decreased, the soft error due to the &agr; particles can happen with higher probability. Therefore, it is desired that a capacitor has a reduced size but can keep sufficient capacitance. In order to achieve this purpose, various capacitor structure designs have been proposed, such as a stacked capacitor. However, an efficient method to fabricate a desired capacitor structure is still under developing. A method to fabricate a stack capacitor has been disclosed in U.S. Pat. No. RE36786. However, the method is still not efficient to have the desired capacitance.
SUMMARY OF THE INVENTION
The invention provides a method for fabricating capacitor in a semiconductor device, so as to effectively increase the capacitance of the capacitor. The method includes providing a substrate, which has several conductive structures formed thereon. The conductive structure has a cap layer on top. A doped region is formed in the substrate between the conductive structures. A first dielectric layer is formed over the substrate and the conductive structures. The first dielectric layer is patterned to form an opening between the conductive structures, where the opening exposes the doped region of the substrate, the sidewalls of the conductive structures, and a portion of top surface of the conductive structures. A conductive plug fills the opening. A second dielectric layer is formed over the first dielectric layer and the conductive plug. The second dielectric layer is patterned to form a narrow opening to expose the conductive plug. A conductive bar is formed to fill the narrow opening. The second dielectric layer is removed to expose a sidewall of the conductive bar and a portion of the conductive plug. A dielectric spacer is formed on the sidewall of the conductive bar. A portion of the conductive plug is still exposed. A conductive spacer is formed on the exposed sidewall of the dielectric spacer. The conductive spacer has electric contact with the conductive plug. The dielectric spacer is removed by isotropic etching. Here, the dielectric spacer and the first dielectric layer have different materials so that the desired etching selectivity is set. As a result, the conductive bar and the conductive spacer form the electrode structure to produce more charge storage area. Then, a conformal capacitor dielectric layer is formed over the substrate to at least cover the conductive bar, the conductive spacer, and the exposed portion of the conductive plug. An electrode conductive layer is formed on the capacitor dielectric layer.
In the forgoing, before the capacitor dielectric layer is formed, a typical hemspherical grain (HSG) conductive layer can also be formed on the exposed surface of the conductive bar and the conductive spacer to further increase the charge storage area. The HSG conductive layer preferably is HSG silicon layer. The HSG silicon layer can be formed by forming a blanket HSG layer over the topographic surface of the substrate. An insulating spacer is formed on sidewalls of the conductive spacer and the conductive bar. An etching back process is performed on the HSG silicon layer, using the insulating spacer as the mask. The insulating spacer is then removed. As a result, the remaining portion of the HSG silicon layer is formed on the exposed peripheral surface of the conductive spacer, the conductive bar, and the conductive plug.
In the foregoing, the conductive structure includes, for example, a gate electrode, a world line, or a conductive line. The first dielectric layer includes, for example, a two-layer structure with a lower dielectric layer surrounding the conductive structures, and an upper dielectric layer formed over the first dielectric layer and the conductive structure.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: Re. 36786 (2000-07-01), Fazan et al.
patent: 5854107 (1998-12-01), Park et al.
patent: 6008085 (1999-12-01), Sung et al.
Huang Jiawei
J C Patents
Tsai Jey
Vanguard International Semiconductor Corp.
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