Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-10
2003-12-02
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000
Reexamination Certificate
active
06656784
ABSTRACT:
BACKGROUND
1. Technical Field
Methods for fabricating semiconductor devices are disclosed and, more particularly, methods for fabricating capacitors of semiconductor devices are disclosed.
2. Description of the Related Art
As the integration of memory devices is enhanced and higher capacitance and lower leakage current of capacitors are required, memory devices are changing from oxide-nitride-oxide (ONO) structures to metal-insulator-metal (MIM) structures.
In other words, as memory devices are integrated more and more, a high dielectric layer having a high dielectric constant, such as BLT, BST, and Ta
2
O
5
, is required, and at the same time, a metal having high work function values needs to be used as a top or bottom electrode to reduce leakage current. The metal used for an electrode of a capacitor includes Pt, Ir, Ru, and TiN.
In a semiconductor device whose cell size is less than 0.10 &mgr;m, even if a high dielectric layer is used as a dielectric layer, three-dimensional storage nodes should be formed, or a capacitor should be formed in the concave structure.
FIGS. 1A and 1B
are cross-sectional views showing a conventional method for forming a capacitor. Referring to
FIG. 1A
, a field oxide layer is formed to separate the elements on a semiconductor substrate
11
, and a junction layer
13
, such as source/drain region of a transistor, is formed by injecting impurities into the active region of the semiconductor substrate
11
, which is defined by the field oxide layer
12
. Subsequently, an inter-layer deposition (ILD)
14
is formed on the semiconductor substrate
11
.
Here, the junction layer
13
is either a p-type or a n-type conductor, and word lines, source/drain of transistors, and bit lines (not shown) are already formed prior to the formation of the ILD layer
14
. The semiconductor substrate
11
may be a silicon substrate, doped silicon substrate, or an epitaxial silicon layer.
Thereafter, a photoresist is deposited on the ILD layer
14
, and then patterned by performing light exposure or development. The ILD layer
14
is etched to form storage node contact holes (not shown) that expose part of the surface of the junction layer
13
, using the patterned photoresist (not shown) as a mask. Here, the storage node contact hole is a contact hole where a storage node contact is to be formed to connect the junction layer
13
and the capacitor vertically.
Subsequently, a doped polysilicon layer is deposited on the ILD layer
14
in a chemical vapor deposition (CVD) method until the storage node contact holes are filled up completely, and then polysilicon plugs
15
, which partially fill the storage node contact holes, are formed by performing recess etch-back.
Subsequently, a titanium layer is deposited on the entire surface of the substrate including the polysilicon plug
15
in a physical vapor deposition (PVD) method, and then a titanium silicide layer
16
is formed on the polysilicon plugs
15
by performing a thermal treatment, which induces silicide reaction between the silicon atoms of the polysilicon plugs
15
and the titanium atoms of the titanium layer.
Then, the un-reacted titanium layer is removed by performing wet-etching so as to make the titanium silicide layer
16
remain only on the polysilicon plugs
15
.
Subsequently, a titanium nitride layer
17
is deposited on the ILD layer
14
until the storage node contact holes, in which the titanium silicide layer
16
is formed, are filled up completely. Then, the titanium nitride layer
17
is polished in a chemical mechanical polishing (CMP) method until the surface of the ILD layer
14
is exposed to make the titanium nitride layer
17
remain only on the titanium silicide layer
16
.
According to the process described above, the storage node contact holes are filled up with storage node contacts, in which the polysilicon plug
15
, titanium suicide layer
16
, and titanium nitride layer
17
are deposited in order. The titanium silicide layer
16
is an ohmic contact layer to reduce contact resistance between the polysilicon plug
15
and the titanium nitride layer
17
. The titanium nitride layer
17
is a barrier layer for preventing diffusion between the subsequent bottom electrode and the polysilicon plug
15
.
Subsequently, an etching barrier layer
18
and an oxide
19
that determines the height and shape of the bottom electrode, to be formed subsequently, are formed on the ILD layer
14
including the titanium nitride layer
17
in order.
Here, the etching barrier layer
18
contributes to the uniform etching of the oxide
19
and thereby prevents damage on the ILD layer
14
from excessive dry etching. For this etching barrier layer
18
, a nitride having an excellent etching selectivity with respect to the oxide
19
, such as Si
3
N
4
, is used, and for the oxide
19
, plasma enhanced-tetra ethyl ortho silicate (PE-TEOS) is used.
Thereafter, the oxide
19
is etched first using a mask (not shown) that defines the storage node on the oxide
19
so that the etching process should stop in the etching barrier layer
18
, and then the etching barrier layer
18
is etched to form concave patterns (not shown) that expose the storage node contacts. This provides an electric path between the storage node contact and the bottom electrode, which will be formed later on.
Subsequently, a ruthenium layer
20
is deposited on the entire surface of the oxide
19
including the concave patterns in a CVD method, and then the ruthenium layer
20
on the oxide
19
, except the ruthenium layer found in the concave patterns, is polished in a CMP method or etched back so as to make the ruthenium layer
20
remain only in the concave patterns.
Here, bottom electrodes formed of the ruthenium layer are filled in the concave patterns, and the neighboring electrodes are insulated from each other by performing CMP. Herefrom, the bottom electrodes formed of the ruthenium layer
20
are referred to as ‘Ru-bottom electrodes
20
.’
Referring to
FIG. 1B
, the oxide
19
that supports the Ru-bottom electrodes
20
is wet-etched to expose the upper part and sidewalls of the Ru-bottom electrodes
20
. On the exposed Ru-bottom electrodes
20
, a dielectric layer
21
and a top electrode
22
are deposited in order, and then the top electrode
22
is patterned selectively to complete the capacitor fabrication.
However, as shown in
FIG. 2
, in the conventional method described above, the etching barrier layer
18
and the Ru-bottom electrodes
20
do not have good adhesion to each other due to the use of diluted HF solution (A) in removing the oxide
19
. Therefore, the HF solution (A) permeates into the interface between them and attacks the ILD layer
14
in the lower part of the substrate.
SUMMARY OF THE DISCLOSURE
A method for fabricating a capacitor is disclosed that can prevent etching solution from attacking an inter-layer deposition (ILD) layer, when the oxide that supports bottom electrodes is wet-etched.
A method for fabricating a capacitor is disclosed that can protect storage node contacts from being oxidized in the subsequent thermal treatment.
A disclosed method for fabricating a capacitor comprises: forming an inter-layer deposition layer on a semiconductor substrate; forming a storage node contact connected to the semiconductor substrate in the inter-layer deposition layer; forming a first etching barrier layer, a second etching barrier layer, and a sacrificial layer on the inter-layer deposition layer and the storage node contact sequentially; forming a concave pattern exposing the storage node contact by etching the sacrificial layer, the second etching barrier layer and the first etching barrier layer sequentially; forming a third etching barrier layer on a inner wall of the concave pattern; forming bottom electrode connected to the storage node contact in the concave pattern; removing the sacrificial layer; removing the second etching barrier layer and the third etching barrier layer selectively, and forming an anti-oxidation layer pattern by leaving the third etching barrier layer between the first et
Elms Richard
Hynix Semiconductor Inc
Marshall & Gerstein & Borun LLP
Owens Beth E.
LandOfFree
Method for fabricating capacitors does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating capacitors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating capacitors will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3106079