Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-30
2004-11-16
Karlsen, Ernest (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000, C438S396000, C438S650000
Reexamination Certificate
active
06818497
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor memory device; and more particularly, to a method for fabricating a capacitor of a semiconductor memory device using an electrochemical deposition.
DESCRIPTION OF THE PRIOR ART
Semiconductor memory devices are generally classified with a random access memory (RAM) and a read only memory (ROM). Specifically the RAM is classified with the a dynamic random access memory (DRAM) and a static random access memory (Static RAM). The DRAM which comprises one transistor and one capacitor in a unit cell, has an advantage in the integration. Therefore, the DRAM has the largest market share in a field of the memory devices.
Acceleration in integration scale of a semiconductor memory device has led a memory capacitance to be augmented by fourfold for every three years. This acceleration has currenty advanced a state of achieving mass production of DRAMs with 256 mega bit or one giga bit.
The area of unit cell and the capacitor should be reduced to less than 0.5 ▾
2
and 0.3 ▾
2
respectively, in case of 256M DRAM.
For this reason, the conventional techniques for the fabrication of the memory devices have limitations to be adopted to the memory device above the 256M devices. In case of fabricating a capacitor in 64M DRAM with use of the conventional dielectric material such as SiO
2
and Si
3
N
4
, the capacitor area should be over six times than the cell area even though the thickness of a dielectric layer in the capacitor can be reduced as thin as possible in order to obtain required capacitance.
Researches for increasing the surface area of the capacitor has been developed. A three-dimensional stack capacitor, a trench type capacitor and a hemispherical type capacitor are introduced to increase the surface area of a bottom electrode of a capacitor.
However, it is impossible to increase the capacitance by more reducing the thickness of the dielectric layer of the capacitor in a devices above 256M DRMA in case of using a material of oxide nitride oxide (ONO). Also, it is impossible to increase the capacitance by fabricating a capacitor having more complicate structure, because the cost is increased as the number of processes to fabricate the complicate capacitor structure.
A high dielectric material such as Ta
2
O
5
, (Ba,Sr)TiO
3
, Al
2
O
3
, SrTiO
3
or TaON is used to form the dielectric layer of the capacitor instead of ONO having lower dielectric constant than the high dielectric material.
The dielectric constants of the high dielectric material vary in accordance with a material of the bottom electrode the capacitor. According to researches up to the present, the excellent dielectric characteristic of the dielectric layer of the capacitor can be obtained in case that the high dielectric material is deposited on a bottomed electrode formed with metal. Therefore, metal such as Pt, Ir, Rh or Ru is used to formed the bottom electrode instead of polysilicon.
A conventional method for fabricating a capacitor in a semiconductor device is described referring to
FIG. 1A
to FIG.
1
E.
Referring to
FIG. 1A
, an first interlayer insulating layer
11
is formed over a semiconductor substrate
10
on which transistors (not shown) and bit lines (not shown) are already formed. The first interlayer insulating layer
11
is etched to form a contact hole exposing a portion of the semiconductor substrate
10
.
Referring to
FIG. 1B
, a polysilicon layer is formed on the interlayer insulating layer
11
including the contact hole, and an etch back process is applied to form a polysilicon plug
12
in the contact hole. Then, a titanium layer is formed and a rapid thermal process (RTP) is performed to form a titanium silicide
13
on the polysilicon plug by inducing a reaction between silicon atoms in the polysilicon plug and the titanium layer. The titanium silicide layer
13
forms an Ohmic contact between the polysilicon plug
12
and a bottom electrode. Thereafter, a titanium nitride layer
14
is formed and removed until a surface of the first interlayer insulating layer is exposed with a chemical-mechanical polishing or an etch back. The titanium nitride layer
14
prevents diffusion of material polysilicon plug
12
and the bottom electrode for a thermal process. The titanium nitride layer
14
also prevents oxygen.
Referring to
FIG. 1C
, a sacrificial layer
15
is formed on a resulting structure including the first interlayer insulating layer and the titanium nitride layer
14
. A trench
16
is formed in the sacrificial layer
15
through a mask formation process and an etch process.
Referring to
FIG. 1D
, a Ru bottom electrode
17
is formed on the sacrificial layer
15
including the trench with MOCVD deposition.
Referring to
FIG. 1E
, the Ru bottom electrode
17
is selectively removed in order that the Ru bottom electrode
17
is left only in the trench.
Referring to
FIG. 1F
, a high dielectric layer
18
and a top electrode
19
are formed to form a capacitor.
The structure of Ru bottom electrode
17
formed is coarse, because the Ru bottom electrode
17
is formed at a low temperature with the MOCVD. A RTP process is applied to the Ru bottom electrode
17
in order to densify the structure of the Ru bottom electrode
17
. However, cracks are generated in the Ru bottom electrode
17
during the RTP.
Portion of titanium nitiride layer
14
are exposed by the cracks in the Ru bottom electrode
17
, and a low dielectric layer is formed and oxidized during a following thermal process. Therefore, the characteristics of the capacitor are deteriorated. The above mentioned problem can be overcome with the limitation that the Ru bottom electrode
17
is formed at the low temperature for improving the step coverage of the Ru bottom electrode
17
.
In addition, the thickness of the Ru bottom electrode
17
should be limited in consideration of the step coverage of a layer covering the capacitor. However, the electric characteristic of the capacitor is deteriorated in case of forming reducing the thickness of the Ru bottom electrode
17
excessively. Therefore, a new process is needed to overcome the above mentioned limitations.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method fabricating a capacitor in a semiconductor memory device capable of improving step coverage a layer and electric characteristic of a capacitor.
In accordance with an aspect of the present invention, there is provided a method for fabricating a capacitor, comprising: forming a contact hole in an insulating layer formed on a substrate; forming a plug in the contact hole, wherein the plug contains a nitride layer; forming a seed layer on the insulating layer and in the contact hole; forming a sacrificial layer including a trench overlapped with the contact hole; forming a Ru bottom electrode in the trench with electrochemical deposition; removing the sacrificial layer and exposing the Ru bottom electrode, wherein the seed layer not covered with the Ru bottom electrode is exposed; removing the exposed seed layer; forming a dielectric layer on the Ru bottom electrode; and forming a top electrode on the dielectric layer.
In the present invention a Ru layer for a bottom electrode of a capacitor is formed with an electrochemical deposition instead of a metal organic vapor deposition. The Ru layer formed with the electrochemical deposition is hard and resistant to erosion. Also, the Ru layer formed electrochemical deposition has low resistance and is appropriate to use in the capacitor.
In case of using the electrochemical deposition, a layer is selectively formed on an exposed conductive layer, and it is possible to obtain good step coverage. Moreover, an electrolyte used to the electrochemical deposition can be recycled, therefore the electrochemical deposition has an advantage in cost compared to a metal organic chemical vapor deposition (MOCVD).
A good surface step coverage obtained by a chemical vapor deposition can be obtained with the electrochemical deposition. Like a s
Choi Hyung-Bok
Song Chang-Rock
Hynix Semiconductor INC
Jacobson & Holman PLLC
Karlsen Ernest
Sarkar Asok Kumar
LandOfFree
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