Method for fabricating capacitor of semiconductor memory device

Details Method for fabricating capacitor of semiconductor memory device Method for fabricating capacitor of semiconductor memory device

2002-06-12

2003-10-21

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S381000

Reexamination Certificate

active

06635524

ABSTRACT:

This nonprovisional application claims priority under 35 U.S.C. §119(a) on patent application Ser. No. 2001-32688 filed in Korea on Jun. 12, 2001, which is herein incorporated by reference.
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor memory device; and more particularly, to a method for fabricating a capacitor of the semiconductor memory device.
BACKGROUND OF THE INVENTION
A Dynamic Random Access Memory (DRAM) cell is a semiconductor memory device typically including one transistor and one capacitor, in which one bit of data is stored in a cell by using an electric charge.
A capacitor has a lower electrode, a dielectric layer, and an upper electrode. One electrode of the lower electrode and the upper electrode is connected to the source/drain junction of the transistor, and the other electrode is connected to a reference voltage line.
As the integration of the DRAM is increased, the size of the memory cell is decreased. However, it is impossible to reduce the size of the memory cell in proportion to the reduction of the DRAM size, because an adequate amount of the capacitance is needed to prevent soft error and to maintain stable operation. There have been efforts to obtain the adequate capacitance by reducing the thickness of the dielectric layer, increasing the effective area and using material having high dielectric constant.
The dielectric layer of a conventional capacitor is formed with a SiO
2
layer, a nitride-oxide (NO) layer or an oxide-nitride-oxide (ONO) layer. The NO layer and the ONO layer are formed with Si
3
N
4
of which the dielectric constant is two times as high as that of the SiO
2
layer.
However, it is impossible to get high capacitance from the SiO
2
layer, Si
3
N
4
layer, NO layer and ONO layer because of the relatively low dielectric constant of the dielectric layers, even though the thickness of the dielectric layers are reduced and the areas are increased. Therefore, dielectric layers, such as (Ba, Sr) TiO
3
(hereinafter referred as “BST”) layer, (Pb, Zr) TiO
3
(hereinafter referred as PZT) layer and Ta
2
O
5
layer, having high dielectric constant are used as a dielectric layer of the capacitor.
The dielectric constant of the Ta
2
O
5
is about 20 to 25, which is three times as high as that of the Si
3
N
4
. Further, it is relatively easier to etch the Ta
2
O
5
layer than the BST layer and PZT layer. Also, the Ta
2
O
5
layer formed by the chemical vapor deposition (CVD) method has a beneficial characteristic of step coverage. However, it is difficult to compose the Ta
2
O
5
layer with the proper stoichiometry. Therefore, recently, the TaON layer has been suggested to overcome the stoichiometry problem of the Ta
2
O
5
layer.
The characteristic of the Ta
2
O
5
layer depends on the electrodes of a capacitor. A capacitor with a Ta
2
O
5
layer as a dielectric layer has a MIS structure. Herein, “M” is a metal layer for forming the plate line; “I” is an insulating layer i.e., the dielectric layer of the capacitor; and, “S” is a polysilicon layer for forming storage electrode. The plate line of the capacitor having the Ta
2
O
5
layer also may be formed with stacked layers of polysilicon layer/TiN layer or polysilicon layer/WN layer. The storage electrode also may be formed with a polysilicon layer of which the surface is treated with nitrogen by the rapid thermal nitration (RTN) process.
In a Metal/Insulator/Silicon (MIS) structure, the thickness of Ta
2
O
5
can be reduced to secure proper capacitance needed in a highly integrated circuit device. Thermal treatment performed after the formation of the capacitor is important when considering a reduction in the thickness of the Ta
2
O
5
layer. That is, the thermal burdens of subsequent processes are less, so it is possible to make a relatively thinner Ta
2
O
5
layer. The minimum thickness of the Ta
2
O
5
layer is not clearly proven, but the limit is presumed to be about 20-30 Å. If thickness of the Ta
2
O
5
layer is decreased more than the limit, the problem of the increasing leakage current occurs.
In order to reduce the thickness of the dielectric layer, the lower electrode may be formed with metal instead of polysilicon. When the lower electrode is formed with metal, the natural oxide, which becomes a disturbance to reducing the thickness of dielectric layer, is not formed on the surface of the lower electrode. Accordingly, it is possible to reduce the thickness of Ta
2
O
5
layer by forming the lower electrode with metal instead of polysilicon.
However, the characteristic of the leakage current is influenced greatly by the quality of the lower electrode when the lower electrode is made with metal. Accordingly, a barrier layer should be formed under the lower electrode to prevent the reaction between the metal layer and the polysilicon plug (or a silicon substrate) and to prevent the diffusion of the oxygen used as a source for forming a dielectric layer, when the lower electrode is made with a metal layer.
In the meantime, the dielectric characteristic of a tantalum-contained-oxide layer, such as Ta
2
O
5
and TiON, depends on the material of the upper electrode.
The TiN layer is relatively stable among the conductive materials, and the TiN layer has adequate step coverage because the TiN layer can be formed by the chemical vapor deposition method. Therefore, the TiN layer is widely used to form the upper electrode.
In the case of forming the upper electrode with TiN, the good electric characteristic of a capacitor can be obtained by the TiN layer formed at a relatively low temperature rather than at a relatively high temperature. However, if the TiN layer is formed at a low temperature, the tantalum-contained-oxide layer, such as Ta
2
O
5
and TiON, is damaged by Cl radical generated by the source material TiCl
4
. In addition, the structure of the TiN layer formed at a low temperature is not dense, allowing deoxidized Ta elements to remain at the interface between the tantalum-contained-oxide layer and the TiN layer. Also, the leakage current caused by the Ta elements deteriorates the electric characteristic of the capacitor.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method of forming a capacitor having a tantalum-contained-dielectric layer.
It is, therefore, another object of the present invention to provide a method of forming a capacitor capable of obtaining good electric characteristic and reducing damage resulting from Cl radicals.
In accordance with one embodiment of the present invention, there is provided a method of forming capacitor of semiconductor device, including the steps of: forming a lower electrode on a semiconductor substrate; forming a dielectric layer containing Ta element on the lower electrode; forming a nitride layer on the dielectric layer by performing a nitrogen plasma treatment; depositing a first TiN layer for a top electrode on the nitride layer by using a plasma enhanced chemical vapor deposition (PECVD) method; and depositing a second TiN layer for the top electrode on the first TiN layer by using a low pressure chemical vapor deposition (LPCVD) method.
In accordance with a second embodiment of the present invention, there is provided a method of forming a capacitor of a semiconductor device including the steps of: forming a lower electrode on a semiconductor substrate; forming a dielectric layer containing a Ta element on the lower electrode; forming a nitride layer on the dielectric layer; depositing a first TiN layer for a top electrode on the nitride layer; and depositing a second TiN layer for the top electrode on the first TiN layer.
In accordance with a third embodiment of the present invention, there is provided present a capacitor for a semiconductor device that includes a semiconductor substrate; a lower electrode over the substrate; a dielectric layer over the lower electrode; an upper electrode over the dielectric layer having a first layer and a second layer; and a nitride layer between the dielectric layer and the upper electrode.
These

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