Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-11-30
2002-10-15
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S396000, C438S964000
Reexamination Certificate
active
06465301
ABSTRACT:
RELATION APPLICATION
The present application claims the benefit of Korean Patent Application No. 2001-23397 filed Apr. 30, 2001, which is herein fully incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular to a method for fabricating a capacitor of a semiconductor device, which can easily adjust a capacitance of the capacitor, and which can solve a bridge problem between the capacitors.
2. Description of the Background Art
In general, memory products have been highly integrated due to development of miniaturized semiconductor technologies. Due to this development, an area size of a unit cell and an operation voltage level are remarkably reduced.
In spite of the decreased cell area, a capacitance over 25fF/cell is required to prevent generation of a soft error and reduction of refresh time.
As in a conventional nitride/oxide (NO) film structure, a DRAM capacitor using a nitride film as a dielectric substance forms a lower electrode in a three-dimensional shape or increases a height of the lower electrode in order to increase an effective area and obtain a sufficient capacitance.
However, a process for forming the lower electrode in a three-dimensional shape is complicated, and thus it is difficult to obtain a sufficient capacitance in the conventional DRAM capacitor.
On the other hand, in a process for increasing a height of the lower electrode, a depth of focus is not obtained in a succeeding exposure process due to a stepped portion between a cell region and a peripheral circuit region which is generated by the increased height of the lower electrode. This problem affects the operation of the capacitor
In order to solve the foregoing problems, there has been suggested a method for forming an uneven hemi-spherical grain (HSG) structure on the surface of the lower electrode. However, the HSG structure generates a bridge problem between the lower electrodes, which results in reduced reliability of the device.
A conventional method for fabricating a capacitor of a semiconductor device will now be described in detail with reference to
FIGS. 1
to
7
.
FIGS. 1 through 5
are cross-sectional diagrams illustrating sequential steps of the conventional method for fabricating the capacitor of the semiconductor device.
FIGS. 6 and 7
show generation of a bridge between lower electrodes, in the conventional method for fabricating the capacitor of the semiconductor device.
As illustrated in
FIG. 1
, an interlayer insulating film
3
is deposited on a semiconductor substrate
1
, and a photoresist film pattern (not shown) exposing a presumed lower electrode contact region is formed on the interlayer insulating film
3
.
The interlayer insulating film
3
is selectively removed by using the photoresist film pattern as a mask, to partially expose the semiconductor substrate
1
.
Thereafter, the photoresist film pattern is removed, and a polysilicon layer is deposited on the interlayer insulating film
3
including the exposed portions of the semiconductor substrate
1
. The polysilicon layer is etched to remain merely in the exposed portions of the semiconductor substrate
1
, thereby forming a contact plug
5
as a lower electrode contact.
A nitride film
7
as an etch barrier film is formed over the resultant structure, and an oxide film
9
is deposited on the nitride film
7
.
Referring to
FIG. 2
, a photoresist film (not shown) is coated on the oxide film
9
, and selectively patterned according to exposure and development processes of a photolithography process, thus forming a photoresist film pattern
11
for a lower electrode pattern for forming a capacitor.
The oxide film
9
and the nitride film
7
are selectively removed by employing the photoresist film pattern
11
as a mask, to form contact holes
12
partially exposing the interlayer insulating film
3
including the contact plug
5
.
As depicted in
FIG. 3
, the photoresist film pattern
11
is removed, a polysilicon layer
13
and an SOG film
15
are sequentially deposited over the resultant structure including the contact holes
12
, and the SOG film
15
is selectively removed according to an etch back process.
As illustrated in
FIG. 4
, the polysilicon layer
13
is selectively removed by using the residual SOG film
15
a
as a mask, until the top surface of the oxide film
9
is exposed. As a result, a polysilicon layer pattern
13
a
is formed.
As shown in
FIG. 5
, the residual SOG film
15
a
and the oxide film
9
are removed. When the oxide film
9
is completely removed, an uneven HSG structure
17
is formed on the polysilicon layer pattern
13
a
according to an HSG process, thereby forming a profile of the lower electrode.
Although not illustrated, a dielectric film (not shown) and an upper electrode (not shown) are sequentially formed on the HSG structure
17
, and thus the fabrication of the capacitor of the semiconductor device is finished.
However, in the conventional method for fabricating the capacitor, a big HSG structure is required to increase a capacitance. As the size of the HSG structures increases, bridges are formed between adjacent HSG structures. For example, as shown in
FIGS. 6 and 7
, a bridge is generated between the adjacent HSG structures in region A due to the lack of a space margin between the lower electrodes, which results in reduced reliability of the device.
Further, poor reliability of the device due to the bridge deteriorates a refresh property and operation of the device.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method for fabricating a capacitor of a semiconductor device, which can improve a refresh property and remove a bridge between adjacent capacitors, by easily adjusting a capacitance.
In order to achieve the above-described and other objects of the present invention, there is provided a method for fabricating a capacitor of a semiconductor device according to an embodiment of the present invention, including the steps of: providing a semiconductor substrate; forming a cylinder type lower electrode by forming a polysilicon layer on the semiconductor substrate; forming a first HSG structure on the inside surface of the cylinder type lower electrode; forming a second HSG structure on the surface of the first HSG structure and the outside surface of the cylinder type lower electrode; forming a dielectric film on the second HSG structure; and forming an upper electrode on the dielectric film.
In another aspect of the present invention, a method for fabricating a capacitor of a semiconductor device includes the steps of: providing a semiconductor substrate; forming an insulating film having a contact hole on the semiconductor substrate; forming a polysilicon layer and a first HSG structure on the insulating film having the contact hole; forming a cylinder type lower electrode consisting of the polysilicon layer and the first HSG structure, by selectively patterning the polysilicon layer and the first HSG structure until the top surface of the insulating film is exposed; removing the insulating film, and forming a second HSG structure on the first HSG structure and the polysilicon layer which compose the cylinder type lower electrode; forming a dielectric film on the second HSG structure; and forming an upper electrode on the dielectric film.
In still another aspect of the present invention, a method for fabricating a capacitor of a semiconductor device includes the steps of: providing a semiconductor substrate; forming a first interlayer insulating film on the semiconductor substrate; forming a first contact hole by selectively patterning the first interlayer insulating film; forming a contact plug in the first contact hole to electrically contact the semiconductor substrate; forming a second interlayer insulating film on the first interlayer insulating film including the contact plug; forming a second contact hole to expose a lower electrode region of the first interlayer insulating film including the contact plug, b
Birch & Stewart Kolasch & Birch, LLP
Chaudhuri Olik
Huynh Yennhu B.
Hynix / Semiconductor Inc.
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