Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-29
2002-03-12
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S393000, C438S252000, C438S253000, C438S254000, C438S394000, C438S003000
Reexamination Certificate
active
06355519
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a capacitor of a semiconductor device having a dielectric layer with higher dielectric characteristic than a conventional nitride/oxide deposition structure of a dielectric layer by forming an alumina (A
203
) layer in a perovskite structure (Al+B5+O3) of superior electrical and mechanical strength.
2. Description of the Prior Art
As integration of a semiconductor memory device gets higher, the size of cells gets smaller. Therefore, it is more and more difficult to secure sufficient capacitance that is in proportion to the surface area of storage nodes.
Particularly, in case of a DRAM device constructed with one MOS transistor and capacitor in a unit cell, it is a key factor for high integration of a DRAM device to reduce the size of a chip while capacitance of a capacitor, occupying a large area of a chip, is kept large.
Thus, in order to increase capacitance C of the capacitor indicated by (&egr;
0
×&egr;
r
×A)/T (where, &egr;
0
is a vacuum dielectric constant, &egr;
r
is a dielectric constant of a dielectric layer, A is area of storage nodes, and T is a thickness of the dielectric layer.), there have been a variety of methods such as use of a material with a high dielectric characteristic for a dielectric layer, formation of a thin dielectric layer, or increase in the surface area of storage nodes.
FIG. 1
is a cross-sectional view for illustrating a method for fabricating a capacitor of a semiconductor device in accordance with the prior art. A Ta2O5 layer is deposited for forming a dielectric layer.
First of all, a lower insulating layer
33
is formed on a semiconductor substrate
31
. At this time, even if it is not shown in
FIG. 1
, the lower insulating layer
33
is constructed with device isolation insulating layer, gate oxide layer and gate electrode or bit line. In addition, an insulating material like Boro Phospho Silicate Glass (hereinafter referred to as BPSG) can be also used for formation of the lower insulating layer
33
.
Then, a contact mask (not shown) is used for an etching process of forming contact holes
35
to expose impurity diffusion regions at predetermined portions of the substrate
31
.
Accordingly, storage nodes
37
are formed for being connected with predetermined portions of the substrate
31
through the contact holes
35
.
Furthermore, a dielectric layer is formed in the oxide layer
39
itride layer
41
deposition structure.
Next, an upper electrode, a plate electrode is formed on the dielectric layer.
Then, an inter-level insulating layer
45
is formed at the top part of the capacitor to further perform the other following processes.
At this time, since the dielectric layer in the deposition structure of oxide layer
39
itride layer
41
proves unsuitable for a highly integrated semiconductor device, it has been replaced with a Ta2O5 layer in recent years. The Ta2O5 layer is deposited in a LPCVD method with a superior step coverage rate.
However, as the Ta2O5 layer has an unstable stoichiometry, some substitution type Ta vacancy atoms inevitably remain in the dielectric layer due to a difference in the composition ratio of Ta and O. Furthermore, in the process of forming the Ta2O5 dielectric layer, an organic material of Ta(OC2H5)5, a precursor of Ta2O5 and O2 (or N2O) gas are reacted to release co-existing carbon atoms, carbon compounds and water.
Therefore, it is difficult to put the Ta2O5 layer into actual use for the dielectric layer because it increases current leakage of a capacitor and deteriorates dielectric characteristic due to impurities like carbon atoms, ions, radicals remaining in the Ta2O5 dielectric layer
41
.
As described above, there is a problem in the conventional method for fabricating a capacitor of a semiconductor device in that it is difficult to actually apply the Ta2O5 dielectric layer for fabrication of a highly integrated semiconductor device due to current leakage and inferior dielectric characteristic.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to solve the aforementioned problem and provide a method for fabricating a capacitor of a semiconductor device, in which a dielectric layer is formed with dielectric characteristic lower than a Ta2O5 layer, but enabling to oppress oxidation reaction occurring at the interface between upper and bottom electrodes through a first stage annealing process, so that an equivalent oxide layer of a dielectric layer is adjusted in thickness of less than 30 angstrom to secure capacitance large enough for high integration to thereby produce a capacitor of a semiconductor device with mechanical and electrical stability.
In order to accomplish the aforementioned objects of the present invention, there is provided a method for fabricating a capacitor of a semiconductor device comprising the steps of: forming storage nodes for being connected with predetermined portions of a semiconductor substrate; forming a surface nitride layer by performing a surface nitrification process to the storage nodes; forming an alumina dielectric layer on the surface nitride layer through a double stage deposition process; and forming a plate electrode on the dielectric layer.
In the method for fabricating a capacitor of a semiconductor device in accordance with the present invention, a dielectric layer is made of an alumnia layer with dielectric characteristic higher than a N/O or O/N/O structure, but lower than Ta2O5 layer, enabling to oppress the oxidation reaction occurring at the interface between upper and bottom electrodes through a first stage annealing process, so that an equivalent oxide layer of a dielectric layer can be adjusted in thickness of less than 30 angstrom to impose high capacitance and that an alumina layer is made as the dielectric layer in a perovskite structure of covalent bonds with high structural stability.
On the other hand, due to unstable stoichiometry of the Ta2O5 layer, there may partially be oxygen vacancy state of substitution type Ta vacancy atoms. Particularly, the number of oxygen vacancies in the Ta2O5 layer can be varied depending on the quantity and bonding state of components, but it is impossible to completely eliminate the oxygen vacancies.
Furthermore, as the Ta2O5 layer has a high oxidation reactivity with a polysilicon or TiN used for upper and bottom electrodes, the oxygen atoms present in the Ta2O5 layer move to the bordering surface to result in an oxide layer of inferior dielectric characteristic and homogeneity.
However, the aforementioned problem can be solved in the present invention by using an aluminum compound for forming a dielectric layer. For instance, at a first stage of the alumina deposition process, an amorphous anumina layer of less than 20 angstrom is placed and annealed for a first stage single-crystallization. Thus, if the alumina layer is formed in a desired thickness, the single-crystallized layer plays a role as a diffusion blocking wall to oxidants, thereby preventing the oxidants from oxidizing the bordering surface with the bottom electrode of a polysilicon layer in the following process.
In consequence, the aforementioned single-crystallization process of the alumina layer fundamentally prevents formation of an oxide layer with inferior dielectric characteristic, as the thickness of an equivalent oxide layer of the capacitor is adjusted less than 30 angstrom. In addition, neither a natural oxide layer elimination process applied to the N/O structure of a capacitor, nor the bottom and the top oxidation processes applied to the O/N/O structure of a capacitor is required to reduce the level of current leakage and secure high capacitance. Also, no low temperature thermal process like in-situ or ex-situ plasma annealing process or ex-situ UV ozone annealing process that has been applied for forming the Ta2O5 layer deposition structure of a capacitor is not required in the present inventi
Crompton Seager & Tufte LLC
Kennedy Jennifer M.
Niebling John F.
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