Method for fabricating capacitor in dram cell

Details Method for fabricating capacitor in dram cell Method for fabricating capacitor in dram cell

1999-07-21

2001-11-20

Bowers, Charles (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S396000, C438S672000, C438S626000, C438S256000

Reexamination Certificate

active

06319768

ABSTRACT:

This Application claims the benefit of Korean Application No. 36576/1998 filed on Sep. 4, 1998, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a capacitor in a highly integrated DRAM cell.
2. Background of the Related Art
As semiconductor memories are developed from mega class to giga class, the cell size reduces and the semiconductor fabrication process gets very complicated. A related art method for fabricating a capacitor in a giga class DRAM cell will be explained in detail with reference to the attached drawings.
FIGS. 1
a
~
1
d
illustrate plan views of DRAM cells showing the steps of the related art process for fabricating a capacitor in the DRAM cell, and
FIGS. 2
a
~
2
e
illustrate section views across lines I-I′ showing the steps of the related art process for fabricating a capacitor in the DRAM cell.
Referring to
FIGS. 1
a
and
2
a
, an active region
2
and a field region (i.e., a region excluding a the active region
2
) are first defined on a semiconductor substrate
1
and a field oxide film
3
is formed on the field region. A plurality of wordlines (i.e., gate electrodes)
4
and cap insulating films (not shown) are formed on the semiconductor substrate
1
perpendicular to the active region
2
at fixed intervals such that every action region
2
has two wordlines passing across the active region
2
. The wordlines
4
are used as masks in injecting impurity ions into the active region
2
to form source/drain impurity regions (not show). Sidewall insulating films
5
are formed at both sides of the wordlines
4
.
As shown in
FIGS. 1
b
and
2
b
, polysilicon is deposited on an entire surface of the substrate, and then selectively removed by a chemical mechanical polishing process (CMP) to expose a surface of the cap insulating film on the wordline. The polysilicon layer is then subjected to patterning by photolithography, and a plurality of first plugs
6
and
6
a
are formed on the active region
2
between wordlines
4
. As shown in
FIG. 1
b
, the first plug
6
a
formed between two adjacent wordlines
4
in each active region is extended to portions at which a bitline is to be formed.
As shown in
FIGS. 1
c
and
2
c
, a thick interlayer dielectric film (ILD) (e.g., a thick oxide film)
7
is formed on an entire surface, and then planarized. A contact hole
8
is then formed in a portion of the first plug
6
a
which is extended to the bitline. A tungsten layer and a cap insulting film are deposited on the entire surface of the substrate, subjected to patterning by photo etching to form a bitline
9
and a cap insulating film
10
in a direction perpendicular to the wordline. An insulating film is deposited on the entire surface, and etched back to form insulating sidewalls
11
at both sides of the bitline
9
, and to expose surfaces of the first plugs
6
and
6
a
by making a slight over etching of the insulating film in the etch back of the insulating film such that the interlayer dielectric film
7
on the first plugs
6
and
6
a
is partially removed.
As shown in
FIGS. 1
d
and
2
d
, polysilicon is deposited on an entire surface, removed by CMP to expose a surface of the cap insulating film
10
on the bitline
9
. The polysilicon layer is then subjected to patterning by photolithography to leave the polysilicon only on the first plug
6
, thus forming a second plug
12
. Referring to
FIG. 2
e
, a storage electrode
13
of a capacitor is formed on the second plug
12
. A dielectric film
14
is formed on a surface of the capacitor storage electrode
13
, and a plate electrode
15
is then formed on the dielectric film
14
, thus completing a capacitor.
The related art method for fabricating a capacitor in a DRAM cell has the following problems. Because two plugs are formed, the related art method has many fabrication steps. In addition, the storage electrode of the capacitor has to be patterned by photolithography. This further complicates the fabrication process.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for fabricating a capacitor in a DRAM cell that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method of forming a capacitor in a DRAM cell so that the storage electrode of the capacitor is formed without using a photolithography process.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method for fabricating a capacitor in a DRAM cell includes the steps of (1) forming a plurality of wordlines each having a cap insulating film on a semiconductor substrate, (2) forming source/drain impurity regions in an active region of the semiconductor substrate on both sides of the wordline, (3) forming first sidewall insulating films at both sides of each of the wordlines, (4) forming a first plug for contact to a capacitor node and a first plug for contact to a bitline on each of the source/drain impurity regions, (5) forming an interlayer insulating film on an entire surface and forming a contact hole to the first plug for contact to the bitline therein, (6) forming a plurality of bitlines in a direction perpendicular to the wordlines, each of the bitlines being in contact with the first plug for contact to the bitline, and having a first cap insulating film, (7) forming second sidewall insulating films at both sides of the bitline and selectively removing the interlayer insulating film to expose a surface of the first plug, (8) forming a second plug on the first plug for contact to a capacitor node, (9) removing the second cap insulating film to a required depth, (10) forming a capacitor storage electrode on the second plug and the second sidewall insulating film, and (11) forming a dielectric film and a plate electrode on an entire surface.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6010933 (2000-01-01), Cherng
patent: 6025227 (2000-02-01), Sung
patent: 6168987 (2001-01-01), Jeng et al.
patent: 6177307 (2001-01-01), Tu et al.

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