Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-15
2003-04-01
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S381000
Reexamination Certificate
active
06541332
ABSTRACT:
BACKGROUND OF THE DISCLOSURE
1. Field of the Disclosure
The disclosure relates to a method for fabricating a semiconductor device; and, more particularly, to a method for fabricating a capacitor.
2. Description of Related Art
As integration of semiconductor devices has increased, studies have been conducted to increase the charge storage area by forming a capacitor in complicated structures such as cylinders, fins, stacks and hemispheric silicon (HSG), to secure sufficient capacitance. In addition, a dielectric layer of capacitor is formed of materials such as ZrO
2
, Al
2
O
3
, Ta
2
O
5
, SrTiO
3
, (Ba,Sr)TiO
3
, BLT, etc, which have dielectric constants that are higher than SiO
2
or Si
3
N
4
. In particular, ZrO
2
layer is a high dielectric layer currently studied for a dielectric layer of a capacitor.
FIGS. 1A
to
1
C are cross-sectional views illustrating a conventional method for fabricating a capacitor.
Referring to
FIG. 1A
, an interlayer dielectric layer (ILD)
12
is formed on a semiconductor substrate
11
having transistors and bit lines, and a storage node contact mask (not shown) is formed on interlayer dielectric layer (ILD)
12
. After that, a storage node contact hole is formed to expose a predetermined area of the surface of the semiconductor substrate
11
by etching the interlayer dielectric layer
12
with the storage node contact mask.
Subsequently, a polysilicon layer is formed on the entire surface including the storage node contact hole, and then an etch back process is carried out in order to form a polysilicon plug
13
in the contact hole to a predetermined depth.
After that, a titanium silicide (TiSi
2
)
14
and a titanium nitride (TiN) layer
15
are formed on the polysilicon plug
13
. The TiSi
2
14
forms an ohmic contact with a following bottom electrode, and the TiN layer serves as an anti-diffusion layer that prevents oxygen remaining inside the bottom electrode from diffusing into the polysilicon plug
13
, the storage node contact plug, or into the semiconductor substrate
11
.
Referring to
FIG. 1B
, a sacrificial oxide layer
16
that determines the height of the bottom electrode is formed on the interlayer dielectric layer
12
and the TiN layer
15
, and then a storage node mask (not shown) using a photoresist is formed on the sacrificial oxide layer
16
.
Subsequently, the sacrificial oxide layer
16
is selectively etched with the storage node mask to form an opening in which a bottom electrode is aligned with the polysilicon plug
13
to be formed.
Thereafter, a bottom electrode
17
is formed of metal over the surface of the sacrificial oxide layer
16
including the opening. After that, the bottom electrode is made to remain in the opening only through the process of etch-back or chemical mechanical polishing method so that the bottom electrode in the concavity is isolated from the neighboring bottom electrodes.
Referring to
FIG. 1C
, on the entire surface including the bottom electrode
17
, a dielectric layer
18
and a top electrode
19
are formed successively. Here, the bottom electrode
17
, dielectric layer
18
and top electrode
19
are formed by a chemical vapor deposition (CVD) method, and the dielectric layer
18
is mostly made of a high dielectric layer such as ZrO
2
.
In the conventional method described above, a capacitor is formed connected to a plug by using a storage node contact mask.
However, in a dynamic RAM (DRAM) over 4 Gbits that a fine design rule should be applied to, the storage node contact plug and the bottom electrode should not be misaligned. Also, to secure a sufficient capacitance, the height of the bottom electrode should be increased, but there is a difficulty because the plug height for interconnection becomes greater as the height of the bottom electrode increases. In addition, because the isolation gap from the neighboring bottom electrode reduces, the current technology for forming a bottom electrode, dielectric layer and top electrode by the CVD method has reached its limitation, so an atomic layer deposition (ALD) method is under development recently.
However, the ALD method has a shortcoming in that an extra thermal treatment, or plasma treatment should be performed in every step to improve the quality of the layers. This is because the ALD method conducts depositions at a low temperature to improve the step coverage. Therefore, the production cost rises when one uses the ALD method due to complicated processes and the investment required for new equipment.
SUMMARY OF THE DISCLOSURE
In one aspect, the disclosure provides a method for fabricating a capacitor that prevents a rise in the production cost and complexity in production processes caused by performing a deposition and a subsequent treatment thereof whenever a layer is formed.
In another aspect, the disclosure provides a method for fabricating a capacitor that prevents a misalignment in masking or etching processes for connecting transistors and the capacitor.
In accordance with an aspect of the disclosure, a method for fabricating a capacitor comprises the steps of: forming a Ti
1-x
Zr
x
N layer on a substrate, wherein x is in the range of 0 to 0.5, inclusive; forming an electrode layer on the Ti
1-x
Zr
x
N layer; and forming a ZrO
2
layer on an interface between the electrode layer and the Ti
1-x
Zr
x
N layer by performing a thermal treatment in an atmosphere containing oxygen gas, whereby a capacitor including a bottom electrode formed with the Ti
1-x
Zr
x
N layer, a dielectric layer formed with the ZrO
2
layer, and a top electrode formed with the electrode layer is fabricated.
In accordance with another aspect of the disclosure, a method for fabricating a capacitor comprises the steps of: forming an interlayer dielectric layer on a silicon semiconductor substrate; forming a contact hole that exposes a surface of the semiconductor substrate by selectively etching the interlayer dielectric layer; forming a Ti
1-x
Zr
x
N layer in the contact hole, wherein x is in the range of 0 to 0.5, inclusive; forming an electrode layer on the Ti
1-x
Zr
x
N layer; and forming a ZrO
2
layer on an interface between the electrode layer and the Ti
1-x
Zr
x
N layer by performing a thermal treatment in an atmosphere containing oxygen gas, whereby a capacitor including a bottom electrode formed with the Ti
1-x
Zr
x
N layer, a dielectric layer formed with the ZrO
2
layer, and a top electrode formed with the electrode layer is fabricated.
REFERENCES:
patent: 5338951 (1994-08-01), Argos, Jr. et al.
patent: 5641702 (1997-06-01), Imai et al.
patent: 5907780 (1999-05-01), Gilmer et al.
patent: 6072689 (2000-06-01), Kirlin
patent: 6235594 (2001-05-01), Merchant et al.
Hynix Semiconductor Inc
Marshall Gerstein & Borun
Tsai Jey
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