Method for fabricating and BEOL interconnect structures with...

Details Method for fabricating and BEOL interconnect structures with... Method for fabricating and BEOL interconnect structures with...

2008-03-25

2008-03-25

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S780000, C438S942000, C257SE21235

Reexamination Certificate

active

07348280

ABSTRACT:
A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in the first ILD. The columnar air gap structure is created using a two-phase photoresist material for providing different etching selectivity during subsequent processing.

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patent: 6903001 (2005-06-01), Bhattacharyya et al.
patent: 7018918 (2006-03-01), Kloster et al.
patent: 2007/0212872 (2007-09-01), Daubenspeck et al.

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