Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
1999-01-25
2001-02-20
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S301000, C438S364000
Reexamination Certificate
active
06191052
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of ultra-shallow, low resistance junctions.
2) Description of the Prior Art
As microelectronic device dimensions decrease, the need to produce ultra-shallow (<60 nm) junctions with low resistance becomes essential. However, conventional ion implantation and annealing processes present several obstacles to formation of ultra-shallow lightly doped source and drain regions necessary for acheiving ultra-shallow junctions with low resistance.
One method of forming ultra-shallow lightly doped source and drain regions is to form a screen oxide layer, implant impurity ions through the screen oxide layer, then perform an anneal to drive in the impurity ions. The disadvantage of this process is that it is susceptible to oxygen enhanced diffusion (OED). OED causes “B” ions to diffuse deeper into the silicon substrate when a screen oxide is used even though the implant depth is shallower than without a screen oxide.
Another process used to form lightly doped source and drain regions is to perform an ion implant and pure N
2
drive in without using a screen oxide. This process does not suffer from OED. However, surface dopant loss occurs during the post implant anneal to drive in the impurity ions. Also, due to reduced gate oxide thicknesses associated with reduced scale devices, the lack of a screen oxide can cause gate oxide integrity degradation due to implantation damage.
An alternate approach is to form a screen oxide, perform impurity ion implantation, strip the screen oxide, then anneal to drive in the impurity ions. Since the screen oxide is removed prior to anneal, this process also suffers from surface dopant loss. Although the screen oxide prevents gate oxide degradation due to implantation damage, oxide stipping can also degrade the gate oxide integrity.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,525,529 (Guldi) discloses a screen oxide or screen oxynitride blocking layer and an NH
3
anneal after ion implantation.
U.S. Pat. No. 5,607,884 (Byun) discloses a NH
3
silicide anneal.
U.S. Pat. No. 5,668,024 (Tsai et al.) discloses a conventional S/D anneal.
U.S. Pat. No. 4,386,968 (Hinkel et al.) shows an ion implantation in O
2
.
U.S. Pat. No. 5,296,411 (Gardner et al.) shows a nitridation process to produce reliable oxides.
The following technical literature also provide information on relevant technical developments.
Shishiguchi et al., 33 nm Ultra-Shallow Junction Technology by Oxygen-Free and Point Defect Reduction Process, 1998 Symposium on VLSI Technology Digest of Technology, pp. 134-135 teaches fabrication of ultra-shallow junctions using low-energy ion implantation without a cover-oxide.
Stinson et al., Effects of I/I on Deep Submicron Drain Engineered MOSFET Technologies, IEEE Transactions on Electronic Devices, Vol. 38, No. 3, March 1991, pp. 487-497 examines the effects of ion implantation on gate oxide integrity. While gate oxide degradation is considered insignificant for oxide thicknesses of 7 nm and LDD doses (10E14 cm
2
and lower), the article predicts that gate oxide degradation will increase as scaling down occurs.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating ultra-shallow lightly doped source and drain regions having low resistance.
It is another object of the present invention to provide a method for fabricating ultra-shallow lightly doped source and drain regions which reduces oxygen enhanced diffusion (OED).
It is another object of the present invention to provide a method for fabricating ultra-shallow lightly doped source and drain regions which prevents surface dopant loss.
It is yet another object of the present invention to provide a method for fabricating ultra-shallow lightly doped source and drain regions which prevents gate oxide integrity degradation.
To accomplish the above objectives, the present invention provides a method for fabricating ultra-shallow lightly doped source and drain regions. The process begins by providing a substrate having an exposed undoped area. A screen oxide layer is formed on the undoped area. Impurity ions are implanted into the substrate, in the undoped area, through the screen oxide layer to form lightly doped source and drain regions. A post-implant anneal is performed on the lightly doped source and drain regions using a rapid thermal anneal in a nitrogen containing atmosphere to drive in the impurity ions.
The present invention provides considerable improvement over the prior art. The ultra-shallow lightly doped source and drain fabrication method of the present invention can simultaneously reduce oxygen enhanced diffusion (OED) and eliminate surface dopant loss. As a result lower resistance, ultra-shallow lightly doped source and drain regions are produced. The nitrogen at the interface between the nitrogen containing screen oxide and the silicon acts as a diffusion barrier reducing OED. Because the nitrogen containing screen oxide layer does not have to be removed to reduce OED, it prevents surface dopant loss during post-implant annealing.
Another advantage of the present invention is that the nitrogen containing screen oxide layer prevents gate oxide degradation which can be caused by ion implant damage when no screen oxide layer is used.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings. Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 4386968 (1983-06-01), Hinkel et al.
patent: 5296411 (1994-03-01), Gardner et al.
patent: 5525529 (1996-06-01), Guldi
patent: 5607884 (1997-03-01), Byun
patent: 5668024 (1997-09-01), Tsai et al.
Shishiguchi et al., “33nm Ultra-Shallow Junction Technology by Oxygen-Free and Point-Defect Reduction Process” 0-7803-4700-Jun. 1998.
1998 IEEE pp. 134-135., Symposium on VLSI Technology Digest.
Stinson et al., “Effects of Ion Implantation on Deep-Submicrometer, Drain-Engineered MOSFET Technologies”, IEEE Transactions on Electron Devices, vol. 38, No. 3, Mar. 1991.
Ackerman Stephen B.
Elms Richard
Saile George O.
Smith Brad
Taiwan Semiconductor Manufacturing Company
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