Method for fabricating an NROM memory cell arrangement

Details Method for fabricating an NROM memory cell arrangement Method for fabricating an NROM memory cell arrangement

2008-01-29

2008-01-29

Smith, Zandra V (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S279000, C438S288000, C438S589000

Reexamination Certificate

active

11015747

ABSTRACT:
In the method, trenches (9) are etched and, in between, bit lines (8) are in each case arranged on doped source drain/regions (3). Dopant is introduced into the bottoms of the trenches (9) in order to form doped regions (23), in order to electrically modify the channel regions. Storage layers are applied and gate electrodes (2) are arranged at the trench walls. The semiconductor material at the bottoms of the trenches is etched away between the word lines (18/19) to an extent such that the doped regions (23) are removed there to such a large extent that a crosstalk between adjacent memory cells along the trenches is reduced.

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