Method for fabricating an interconnect line

Details Method for fabricating an interconnect line Method for fabricating an interconnect line

2003-04-07

2004-07-27

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S669000, C438S611000, C438S666000, C438S945000

Reexamination Certificate

active

06767821

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention generally relates to semiconductor substrate processing systems. More specifically, the present invention relates to a method for fabricating an interconnect line of an integrated electronic device.
2. Description of the Related Art
In advanced integrated circuits, a major cause of the circuit delay is a relatively high value of the time constant &Dgr;T=RC of interconnect lines, where R and C are resistance and capacitance of the line per unit length, respectively. Increased capacitance between conductors of the lines degrades performance of integrated electronic devices (e.g., transistors, memory cells, and the like) and, specifically, decreases the propagation speed of electrical signals. Both low inter-line capacitances and low inter-level capacitances are important to alleviating this problem.
To decrease the capacitance, conventional high-speed integrated circuits use dielectric materials having a low dielectric constant (i.e., low-K dielectric materials having a dielectric constant that is less than 2.5-3.0). Such low-K dielectric materials generally comprise carbon doped silicon oxide, organic doped silicon glass (OSG), fluorine doped silicon glass (FSG), and the like.
To develop yet faster electronic devices, capacitance of the interconnect lines should be reduced even further. Using air as a dielectric material is the most effective way to reduce capacitance of an interconnect line and, as such, the RC delay, since the air has a dielectric constant of 1 that is less than the dielectric constant of any other material.
Controlled air gaps (also known in the art as “air bridges”) may be formed beneath a conductor of the interconnect line. Using a conventional technique, the conductor is formed on a sacrificial dielectric layer that then is selectively removed during a dry or wet etch process. However, such a technique poses many integration, reliability, and manufacturability problems that limit the use of air bridges in the integrated circuits.
Therefore, there is a need in the art for an improved method of fabricating an interconnect line having an air bridge.
SUMMARY OF THE INVENTION
A method of fabricating an interconnect line comprises forming a wall of conductive material, depositing an etch mask having a thickness that decreases towards a bottom of the wall, and isotropically etching the wall at the bottom to form the interconnect line having a pre-determined gap between the substrate and a bottom of the line.
In one exemplary embodiment, the wall comprises polysilicon, the etch mask is formed using at least one fluorocarbon gas or hydrofluorocarbon gas (e.g., C
4
F
8
, CHF
3
, and the like), and the etch process uses sulfur hexafluoride (SF
6
) and the like.


REFERENCES:
patent: 2002/0148807 (2002-10-01), Zhao et al.

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