Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-07-24
2003-09-02
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S275000, C438S301000, C438S229000, C438S238000
Reexamination Certificate
active
06613624
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for fabricating an integrated semiconductor circuit.
To ensure proper fabrication to integrated semiconductor circuits, transistors are formed on a semiconductor substrate. Customary transistors are usually MOSFETs (metal oxide semiconductor field-effect transistors) whose central electrode, the gate electrode, is patterned from a sequence of layers deposited on a substrate. The source and drain electrodes are then implanted into the substrate on both sides of the gate electrode. The gate electrode substantially determines the switching behavior of the transistor. The desired switching behavior depends on the task accorded to the transistor. In particular, the circumstance of whether the transistor is a memory transistor of a memory cell or a logic transistor that must satisfy more stringent requirements made of the transistor performance and, under certain circumstances, also process analog signals greatly affects the construction of the transistor, in particular the composition of its gate layer stack.
Adjacent transistors on the substrate surface are usually disposed spatially separate and therefore each has an individual source terminal and a drain terminal. By contrast, transistors for memory cells can be fabricated in pairs at a short distance from one another, their adjacent gate layer stacks being separated only by a narrow region which simultaneously serves as source or drain contact for both transistors. The electrode terminal for the connection of the common electrode is subsequently introduced into the small interspace between the adjacent gate layer stacks. To that end, an etching is preformed in order to be able to electrically contact-connect the common electrode between the adjacent gate layer stacks. During this etching, the gate layer stacks themselves are attacked, which is undesirable. For this reason, the gate layer stacks are protected by a thick nitride layer that is deposited as topmost layer before their actual patterning. During the later etching for contact-connecting the substrate implantations, the nitride layer protects the gate layer stacks overall.
Transistors fabricated in this way can be disposed at a short distance from one another in the regions of the substrate surface that are memory regions, and be provided with a common source or drain terminal, which is referred to as a borderless contact. It is used exclusively in the memory region, where there are less stringent requirements made of the switching behavior of the transistors than in the logic region. Although the same transistors are produced in both regions, they are produced at a small distance from one another in pairs in the memory region, as a result of which, the substrate surface required for a memory cell is reduced. This makes it possible to fabricate particularly small memory cells.
In order to improve the switching behavior of a transistor, it is customary nowadays for the bottommost layers of a gate layer stack to be doped by an ion implantation. Although, unlike in the source and drain electrodes, which are only formed by the introduction of implantations into the substrate, an implantation of the gate electrode is not absolutely necessary since the gate electrode only serves for the generation of an electric field through the gate oxide layer, the electrical potential of the substrate channel region situated beneath the gate layer stack can be optimized if the electrical potential of the gate layer situated above it is altered. In accordance with the band scheme for electronic systems in solids, such a potential shift is effected with the aid of introduced dopings that cause an energetic band shift in the gate electrode. This band shift leads to an alteration of the work function of the electrons in the bottommost gate layer at the boundary with the underlying gate oxide. The electrical potential of the channel region is altered through this altered work function.
The band shift required has a different magnitude depending on the type of transistor. In particular, it may be positive or negative.
N-channel transistors, whose channel is formed by negative charge carriers are provided with an n-type doping of the gate electrode. P-channel transistors, by contrast, receive a p-type doping. In cMOS circuits (complementary MOS), a different doping of n-channel and p-channel transistors is optimal.
Difficulties arise as soon as an integrated semiconductor circuit contains both memory transistors and logic transistors. Many of today's integrated circuits, for example ASICs (application specific integrated circuits), contain memory regions that are surrounded by logic regions and are referred to as embedded DRAMs (embedded dynamic random access memories). Both regions are fabricated by the same fabrication method. In particular, the transistors for both regions are produced by a common method process.
In the memory region, where the memory transistors are to be produced as far as possible in a borderless contact construction, i.e. in pairs with a common electrode between the gate layer stacks, the gate electrode must be protected by a protective layer, typically having a thickness of 200 nm, against the contact hole etching which is required for fabricating a borderless contact. On account of this thick protective layer, implantations cannot subsequently be implanted into the gate electrode. Therefore, doped polysilicon is deposited as bottommost gate layer, e.g. as PSG. As a result, the transistors to be produced in the memory region can be produced in pairs with a borderless contact.
This construction of integrated circuits has the disadvantage in the logic region. The transistors of the logic region are produced at the same time as the transistors of the memory region. In the logic region, the same gate implantation is introduced in all the logic transistors, both in the n-channel transistors and in the p-channel transistors. The gate implantation is coordinated with the memory transistors (usually exclusively n-channel transistors), which are disposed in the memory region. The p-channel transistors that are likewise disposed in the logic region thus receive a negative doping in their gate electrodes, which sets a non-optimal work function of the electrons in their gate layer. The same value of the work function is set between the lower gate layer and the gate oxide in all the transistors of the integrated semiconductor circuit. This construction is referred to as single work function.
This construction is disadvantageous, however, in the logic region.
Particularly in the case of transistors of increasingly smaller dimensioning with a lower operating voltage, the respective optimal adaptation of the work function and thus the dual work function construction become increasingly important.
If, on the other hand, the transistors of the integrated semiconductor circuit are to be produced in a dual work function construction, then two different dopings must be introduced into the bottommost gate layer. The dopings can only be introduced subsequently by implantation. Since these implantations are implanted at the same time as the source/drain dopings, p-channel transistors receive a positive gate doping and n-channel transistors receive a negative gate doping. Two implantation steps are carried out, during which the respective transistors that are not to be implanted are covered by a mask.
The subsequent implantation in the logic region precludes deposition of a predoped gate layer and thus requires a subsequent implantation of the gate electrodes in the memory region as well. However, this means that a close pairwise configuration of transistors with a borderless contact is not possible in the memory region since the thick protective layer over the gate electrodes that is required for the contact hole etching prevents a subsequent implantation. Consequently, the construction of an integrated semiconductor circuit with dual work function, i.e. with two kinds of values of the work function of th
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Picardat Kevin M.
Stemer Werner H.
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