Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-25
2002-01-22
Bowers, Charles (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06340616
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a method for fabricating an integrated electronic circuit, in which electrically active elements are produced in the region of one plane, at least one insulation layer and at least one contact-making layer are applied on the electrically active elements, and subsequently at least one connecting wire is applied to the contact-making layer.
The invention furthermore relates to an integrated electronic circuit, having a plane in which electrically active elements are situated, at least one insulation layer and at least one contact-making layer being applied on the electrically active elements, and at least one connecting wire being applied on the contact-making layer.
It is known to carry out the method of the generic type in such a way that intermediate layers are deposited in order to protect the active elements against any adverse effects during subsequent application of a connecting wire.
U.S. Pat. No. 4,984,061 discloses a placement of the connecting wire above a wiring plane and producing the intermediate layer between the wiring plane and the connecting wire. That method includes patterning the intermediate layer.
Patterning the intermediate layer is also disclosed in U.S. Pat. No. 5,854,507.
U.S. Pat. No. 5,751,965 likewise discloses a method in which a connecting wire is disposed above a wiring plane. In that case, at least three intermediate layers are produced between the wiring plane and the connecting wire.
European Patent Application EP 0 587 442 A2 and an article entitled: Wire Bonds Over Active Circuits, IEEE, 1994, pp. 922-928, by G. Heinen at al., disclose producing an intermediate layer made of polyimide below the contact-making layer.
European Patent Application EP 0 100 100 A2 discloses constructing the intermediate layer from polycrystalline silicon.
U.S. Pat. No. 5,847,448 discloses constructing an integrated electronic circuit of the generic type in a three-dimensional manner.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating an integrated electronic circuit and an integrated electronic circuit, which overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type in such a way that the method can be carried out with the lowest possible outlay, and damage to active elements is avoided when connecting wires are connected to a contact-making layer.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating an integrated electronic circuit, which comprises producing electrically active elements in a region of one plane; applying at least one insulation layer and at least one contact-making layer on the electrically active elements; subsequently applying at least one connecting wire with a given radius to the contact-making layer; and producing the contact-making layer with a thickness of at least 10% of the given radius.
The invention provides for the thickness of the contact-making layer and the dimension of the connecting wire to be coordinated with one another.
In accordance with another mode of the invention, the contact-making layer has a thickness which is at least 15% of the radius of the connecting wire.
In accordance with a further mode of the invention, in order to completely avoid any adverse effects on the active elements as a result of the process of connecting the connecting wire to the contact-making layer, the active elements are disposed in such a way that the contact-making layer is formed as a planar area.
This particularly advantageous embodiment of the invention provides for the connecting wire to be disposed on a sufficiently large planar area above the active elements. This particularly preferred embodiment of the invention includes a combination of technological measures and a targeted configuration of the layout. The structure of the contact-making layer in the form of a planar area is preferably obtained by the individual active elements being formed by sufficiently large transistors, in particular quasi vertical DMOSFET transistors.
In accordance with an added mode of the invention, a further increase in the reliability of the integrated electronic circuit is obtained by producing an intermediate layer in the form of a planar area.
In accordance with an additional mode of the invention, the intermediate layer is interrupted only by contact holes.
In accordance with yet another mode of the invention, an increase in the reliability of the integrated electronic circuit is also obtained by producing at least two further metalization layers in addition to the contact-making layer.
In accordance with yet a further mode of the invention, the contact-making layer is strengthened in the region of the connecting wire. In accordance with yet an added mode of the invention, this is done in a particularly simple and expedient manner by a metal being vapor-deposited in the region of the connecting wire. The vapor-deposited metal preferably has the same composition as the remaining metal of the contact-making layer.
With the objects of the invention in view there is also provided an integrated electronic circuit, comprising electrically active elements disposed in a plane; at least one insulation layer and at least one contact-making layer applied on the electrically active elements; at least one connecting wire with a given radius, the at least one connecting wire applied on the contact-making layer; and the contact-making layer having a thickness of at least 10% of the given radius.
Other features which are considered as characteristics for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating an integrated electronic circuit and an integrated electronic circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
Derwent Abstracted Publication No. DE 19908188A of foreign priority document of the instant application.
Mosig Karsten
Schwetlick Werner
Stecher Matthias
Bowers Charles
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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