Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-05-30
2003-02-25
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S619000, C438S659000
Reexamination Certificate
active
06524917
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method for fabricating an integrated circuit, comprising the following steps: preparing a substrate with an electrically insulating layer above it; providing an interconnect having a lower conductive layer and an upper conductive layer on the insulating layer, the lower conductive layer consisting of silicon of a first conduction type; embedding the interconnect in an electrically insulating structure; at least partially uncovering a second section of the lower conductive layer of the interconnect of the first conduction type and removing the second section by means of an etching process.
RELATED ART
A fabrication method of this type is known from DE 199 06 291 A1 and from U.S. Pat. No. 5,786,253.
In integrated circuits, interconnects are required as wiring to drive the individual circuit components. These interconnects usually also lead over what are known as active regions or other conductive structures, so that parasitic capacitances occur, which have an adverse effect on the speed of the circuit.
Therefore, the two documents DE 199 06 291 A1 and U.S. Pat. No. 5,786,253 have described a fabrication method in which interconnect sections are arranged above a cavity. The lower surface of the cavity adjoins an insulating layer on a substrate, while the upper surface of the cavity adjoins the interconnect and two insulating spacers which lie opposite one another. The spacers also cover the side walls of the interconnects. The cavity usually has substantially the same lateral dimensions as the interconnect and is filled with air or a substantially inert gas or is partially evacuated The fact that the size of the cavity, in particular the undercut etching of the lower layer of the interconnect, can only be controlled with difficulty has proven to be a drawback of the known fabrication method.
Therefore, it is an object of the present invention to provide a fabrication method of the type described in the introduction in which the size of the section which is removed can be controlled more accurately.
According to the invention, this object is achieved by the fabrication method which is described in claim
1
.
The advantages of the method according to the invention reside in particular in the fact that the length of the undercut etching of the interconnect can be accurately set, for example by means of a masking step and an implantation step. This therefore eliminates inaccurate adjustment by means of etching time and etching temperature as in the prior art.
SUMMARY OF THE INVENTION
The idea on which the present invention is based consists in reversing the doping of at least one first section of the lower conductive layer of the interconnect to the second conduction type. This is followed by at least partial exposure of a second section of the lower conductive layer of the interconnect of the first conduction type. Finally, the second section of the lower conductive layer of the interconnect of the first conduction type is selectively etched by the etching process, with the first section acting as an etching stop.
The subclaims describe advantageous developments of and improvements to the method described in claim
1
.
According to a preferred refinement, the second section of the lower conductive layer of the interconnect of the first conduction type is completely removed.
According to a further preferred refinement, the upper conductive layer consists of a metal silicide.
According to a further preferred refinement, the electrically insulating structure has spacers of the interconnect and an electrically insulating layer.
According to a further preferred refinement, the doping reversal comprises the steps of providing a first mask having an opening above the first section and carrying out ion implantation with ions of the second conduction type using the first mask.
According to a further preferred refinement, the uncovering operation comprises the steps of providing a second mask having one or more openings above the second section and removing the electrically insulating structure by means of an etching step using the second mask.
According to a further preferred refinement, the doping of two first sections, between which the second section is located, is reversed.
According to a further preferred refinement, the interconnect is a word line of a semiconductor memory device.
According to a further preferred refinement, two source/drain regions, which are spaced apart from one another, of a select transistor are provided in the substrate, and the second section runs above the channel region between these two source/drain regions.
According to a further preferred refinement, the lower conductive layer consists of polysilicon.
According to a further preferred refinement, the selective etching is carried out by wet-chemical means using KOH.
According to a further preferred refinement, the second section is filled with an electrically insulating layer.
An exemplary embodiment of the invention is illustrated in the drawings and is explained in more detail in the description which follows.
REFERENCES:
patent: 4124933 (1978-11-01), Nicholas
patent: 5000818 (1991-03-01), Thomas et al.
patent: 5786253 (1998-07-01), Hsu
patent: 6054353 (2000-04-01), Sheu et al.
patent: 6127251 (2000-10-01), Gardener et al.
patent: 6204165 (2001-03-01), Ghoshal
patent: 199 06 291 (2000-08-01), None
patent: WO 98/40909 (1998-09-01), None
Chaudhari Chandra
Infineon - Technologies AG
Jenkins & Wilson, P.A.
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