Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-07-01
2001-11-13
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S671000
Reexamination Certificate
active
06316358
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor manufacturing, and more particularly to a method of forming a metal line on an integrated circuit substrate having a step.
BACKGROUND OF THE INVENTION
One of the important technologies for progress in micro-size processing is photolithography. Past progress in this technology resulted from a reduction of the exposing wavelength and high numerical aperture (NA) of a contracting projection lens in a contracting projection exposure device (stepper). The reduction in wavelength and the high NA impose non-meritorious conditions in increasing the depth of focus (DOF) since the DOF is proportional to the exposing wavelength &lgr; and inversely proportional to the square of the numerical aperture NA.
On the other hand, the surface step difference of a semiconductor wafer, as an object to be exposed to light, tends to increase year by year in keeping with high integration density of the semiconductor integrated circuit. The reason is that, under the current technology towards three-dimensional device structure, contraction in the three dimensional direction is not as significant as that in the two-dimensional direction due to necessity in maintaining the performance and reliability of the integrated circuit. If a photoresist material is coated on the surface of a semiconductor wafer having such significant step difference, larger surface step difference or variations in the film thickness are produced on the photoresist layer.
On the other hand, the imaging surface cannot be perfectly smooth due to the presence of distortion in the imaging surface, while the substrate surface is slightly tilted from a surface which is perfectly normal to an optical axis of the projection optical system. These factors render difficult the uniform light exposure of the entire wafer in the sole imaging plane.
FIGS. 1A
to
1
D shows cross-sectional views of an integrated circuit substrate, at selected stages of process steps of forming a metal line, illustrating problems associated with photographic process with respect to uneven top surface topology. Referring to
FIG. 1A
, the integrated circuit substrate is divided into a cell array region “B” and a peripheral region “A”. As can be seen, the integrated circuit substrate has a large step (height difference T
o
) between the cell array region and peripheral region due to previously-formed integrated circuit elements (not shown) such as a capacitor in cell array region “B”. An interlayer insulating layer
10
is formed on the integrated circuit substrate including the integrated circuit elements. A metal layer
12
for metallization is formed on the interlayer insulating layer
10
. As can be seen, the top surface of the metal line follows the contour of the underlying step. The metal layer
12
has a thickness of T
m
both in the lower portion of the step and upper portion of the step. In order to form a metal pattern, a photoresist layer
14
is spin coated on the metal layer
12
. Since the photoresist layer
14
is conformal, the photoresist layer
14
is formed thickly in the lower portion of the step as compared to that in the upper portion of the step (see reference numeral T
l
and T
h
). As a result, height difference between the cell array region and peripheral region is changed from original T
o
to T
f
.
A mask substrate
16
having mask pattern
18
is provided. The size of the mask pattern
18
defines the size of the desired metal line. Further, space between the mask pattern
18
and the next defines the space between the metal line and the next. As can be seen, mask pattern size (Ll) in the lower portion of the step is equal to the space (Sl) between adjacent mask patterns in the lower portion of the step. Mask pattern size (Lh) in the upper portion of the step is equal to the space (Sh) between adjacent mask patterns in the upper portion of the step.
Using the mask substrate
16
and mask pattern
18
, the photoresist layer
14
is exposed to light to form a photoresist pattern
14
a
as shown in FIG.
1
B. If light exposure is insufficient, the photoresist layer
14
in the lower portion of the step (i.e., in the peripheral region) is not completely exposed to the light due to the relatively larger thickness as compared to that in the upper portion of the step (i.e., cell array region). As a result, a portion of the photoresist layer
14
is left in the low portion of the step (i.e., in the peripheral region), thereby causing the so called scum phenomenon or bridge phenomenon. Further, in the case where the light energy is large enough to sufficiently avoid these problems, excessive amounts of light can be applied to the photoresist layer
14
in the upper portion of the step. As a result, other problems arise. For example, the desired pattern may not be obtained due to excessive light exposure and notching phenomenon occurs due to excessive loss of the photoresist layer
14
.
Using the photoresist pattern
14
a
as an etching mask, the conductive layer
12
is etched to form conductive pattern
12
a
as shown in FIG.
1
C. If the conductive layer
12
is not sufficiently selectively etched with respect to the photoresist pattern
14
a
, the photoresist pattern
14
a
is etched simultaneously. For example, partial thickness of the photoresist pattern (T
e
) is etched in the lower portion of the step and all the photoresist pattern
14
a
is etched in the upper portion of the step as shown in FIG.
1
C. More specifically, since the photoresist pattern is thinner in the upper portion of the step than in the lower portion of the step, upper portion of the step is firstly exposed to the light. Accordingly, a partial thickness of the conductive pattern
12
a
(see reference numeral T
me
) can be over-etched, producing the so called notching phenomenon. The resulting conductive pattern
12
a
in the upper portion of the step has a thickness of T
m
-T
me
.
Photoresist layer
14
may be formed very thickly to overcome the above-mentioned problems. The focus margin, however is inversely proportional to the thickness of the photoresist layer
14
, thereby making it difficult to apply practical manufacturing. Alternately, several photolithography processes may be performed with respect to the step so as to obtain an optical conductive pattern. This method also has a problem associated with fabrication cost.
Referring now to
FIG. 1D
, a remainder of the photoresist layer
14
is removed to form conductive pattern
12
a
. Resulting conductive pattern
12
a
, however, has a thickness of T
me
-T
me
in the upper portion of the step.
Accordingly, a method is needed which can form a uniform conductive pattern
12
a
on an integrated circuit substrate having a step without above mentioned problems.
SUMMARY OF THE INVENTION
The present invention was made in view of the above-described problems, and it is therefore an object of the invention to provide a method for forming a uniform conductive pattern on an integrated circuit substrate having a step by the use of a single photography process.
A mask substrate, which is used in the photography process for patterning a photoresist layer, has different pattern sizes according to topology of the integrated circuit substrate. The mask substrate has a relatively wide pattern size and narrow space between adjacent patterns in the upper portion of the step in the integrated circuit substrate as compared to that of the desired conductive pattern. On the other hand, the mask substrate has a relatively narrow pattern size and wide space between adjacent patterns in the lower portion of the step as compared to that of the desired conductive pattern. Such mask pattern allows a uniform conductive pattern regardless of the topology of the integrate circuit substrate.
More specifically, in accordance with the present invention, a method for fabricating an integrated circuit device is formed by providing an integrated circuit substrate. A cell array region and a peripheral region are defined therein. Transistors are formed on both cell array and periph
Cantor & Colburn LLP
Gurley Lynne
Niebling John F.
Samsung Electronics Co,. Ltd.
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