Method for fabricating an embedded dynamic random access memory

Details Method for fabricating an embedded dynamic random access memory Method for fabricating an embedded dynamic random access memory

1999-01-25

2002-01-08

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S981000

Reexamination Certificate

active

06337240

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This applications claims the priority benefit of Taiwan application serial no. 87117426, filed Oct. 21, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating an embedded dynamic random access memory device.
2. Description of Related Art
An embedded dynamic random access memory (DRAM) device is a kind of device that includes a memory array and a logic circuit array formed together in a single integrated circuit (IC) chip. This embedded DRAM therefore can access a large amount of data with much higher accessing speed so that the embedded DRAM with its advantages is widely used in a logic circuit, which is used for a purpose to process a large amount of data, such as a graphic or an image microprocessor. An accomplished embedded DRAM, typically includes a logic circuit, a transfer field effect transistor (transfer FET) array, and a capacitor coupled to the transfer FET, in which the transfer FET serves as a lower electrode of the capacitor and a selective switch when the transfer FET is selected by a bit line. The voltage status of the capacitor can therefore be read or changed through the transfer FET. One FET typically includes a gate structure and an interchangeable source/drain region at each side of the gate structure. The capacitor is coupled to the interchangeable source/drain region at one side of the gate structure, which typically is the source region.
FIGS. 1A-1E
are cross-sectional views of a portion of a semiconductor substrate, schematically illustrating a conventional fabrication process for forming an embedded DRAM. In
FIG. 1A
, an isolation structure
102
is formed on a semiconductor substrate
100
so as to form a DRAM active area
170
and a logic active area
180
on the substrate
100
. A DRAM transfer FET is to be formed on the DRAM active region
170
, and a logic transfer FET included in a logic circuit is to be formed on the logic active region
180
. In order to obtain a smaller gate resistance, a formation of a gate includes depositing a polysilicon layer on the substrate
100
, forming a silicide layer on the polysilicon layer to form a polycide layer, and patterning the polycide layer. An alternative method is first depositing a patterned polysilicon layer on the substrate
100
, performing a self-aligned silicide (Salicide) process to form a Salicide layer on all exposed silicon surface of the patterned polysilicon and an interchangeable source/drain region. However, the Salicide process usually consumes the junction depth to cause a shallow junction, which may further cause a charge leakage of the capacitor. The DRAM device may results in a failure at the end. A strategy combining above two methods is then proposed. In the embedded DRAM, a gate structure is usually formed by a polysilicon layer and a silicide layer through deposition. The interchangeable source/drain region of a transistor belonging to the DRAM is not formed with a Salicide layer so as to avoid the charge leakage. But, the interchangeable source/drain region of a transistor belonging to the logic circuit is formed with a Salicide layer to reduce its sheet resistance so that the logic circuit has faster operation speed. In order to form the Salicide layer only on the logic transistor, a conventional method is described in the following.
In
FIG. 1A
, a usually thin oxide layer
104
is formed over the substrate
100
. A polysilicon layer
106
and a silicide layer
108
are sequentially formed on the oxide layer
104
. This two layers
106
,
108
are usually called together as a polycide layer. A cap layer
110
is formed on the silicide layer
108
.
In
FIG. 1B
, patterning the cap layer
110
, the silicide layer
108
, the polysilicon layer
106
, and the oxide layer
104
forms a gate structure
112
on the DRAM active area
170
of
FIG. 1A
, and a gate structure
114
on the logic active area
180
of FIG.
1
A. The gate structure
112
includes a cap layer
110
a
, a silicide layer
108
a
, a polysilicon layer
106
a
, and the oxide layer
104
a
; and the gate structure
114
includes a cap layer
110
b
, a silicide layer
108
b
, a polysilicon layer
106
b
, and the oxide layer
104
b
. Using the cap layers
110
a
,
110
b
as a mask, an interchangeable source/drain region
128
and an interchangeable source/drain region
130
are respectively forms in the substrate
100
at each side of the gate structure
128
and the gate structure
130
.
In
FIG. 1C
, an annealing process at a temperature of 900° C.-1000° C. is performed to uniformly diffuse the implanted ions so that the interchangeable source/drain regions
128
,
130
become the interchangeable source/drain regions
128
a
,
130
a
. So, each of the DRAM active area
170
an the logic active area
180
of
FIG. 1A
respectively have a formed DRAM FET and a formed logic FET. The DRAM FET includes the gate structure
112
and the interchangeable source/drain regions
128
a
, and the logic FET includes the gate structure
114
and the interchangeable source/drain region
130
a
. A spacer
120
is formed on each sidewall of the gate structure
112
and a spacer
122
is formed on each sidewall of the gate structure
114
. In order to decrease the sheet resistance of the interchangeable source/drain region
130
a
of the logic FET at the logic active area
180
of
FIG. 1A
, a Salicide layer is desired to be formed on the interchangeable source/drain region
130
a
, but not on the interchangeable source/drain region
128
a
of the DRAM FET. A typical process is forming an insulating layer
132
over the DRAM FET. A Salicide process is performed by first forming a metal layer
134
over the substrate
100
.
In
FIG. 1D
, a rapid thermal process (RTP) is performed to trigger a reaction between silicon of the interchangeable source/drain region
130
a
and the metal layer
134
so as to form a Salicide layer
136
on it. Using a mix acid solution of H
2
O
2
and NH
4
OH as an etchant, a wet etching process is performed to remove the metal layer
134
without reaction.
In
FIG. 1E
, a dielectric layer
140
is formed over the substrate
100
. The dielectric layer
140
is patterned to form a contact opening
142
to expose the interchangeable source/drain region
128
a
of the DRAM FET at one side of the gate structure
128
a
. A capacitor
150
including a polysilicon layer
144
serving as a lower electrode, a dielectric film layer
146
, and a polysilicon upper electrode
148
is formed on the dielectric layer
140
. The capacitor
150
is coupled to the DRAM FET through the contact opening
142
. The DRAM FET with the capacitor
150
is accomplished.
In the conventional fabrication method describe above, the thickness of the gate oxide layer
104
a
of the gate structure
112
, shown in
FIG. 1B
, for the DRAM FET is equal to the thickness of the gate oxide layer
104
b
of the gate structure
114
for the logic FET. In an actual operating condition, the DRAM FET is applied with a higher bias than a bias applied on the logic FET. This causes the gate oxide layer
104
a
of the DRAM FET needs to endure a higher bias than the gate oxide layer
104
b
of the logic FET. If the gate oxide layers
104
a
,
104
b
are formed with a greater thickness suitable for the DRAM FET, the logic FET may not be activated. If the gate oxide layers
104
a
,
104
b
are formed with a smaller thickness suitable for the logic FET, the DRAM FET may get a breakdown.
On the other hand, in order to reduce the gate resistance of the gate structure
112
of the DRAM FET and avoid a charge leakage due to shallow junction occurring on the interchangeable source/drain region
128
a
, both gate structures
112
and
114
respectively having the polysilicon layer
106
a
and
106
b
, and the silicide layers
108
a
and
108
b
. In this strategy, even though the gate resistance of the DRAM FET is reduced, the operating performance of the logic F

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