Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1998-10-28
2000-10-17
Whitehead, Jr., Carl
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438275, 438279, 438655, 438664, H01L 213205, H01L 214763
Patent
active
061331309
ABSTRACT:
A method includes a self-aligned silicide (Salicide) technology in fabrication of an embedded dynamic random access memory (DRAM). On a silicon wafer, a first MOS transistor is formed in a logic device region, and second MOS transistor is formed in a memory device region. The improved method includes forming an insulating layer over the substrate at least covering the first (second) MOS transistor. A top portion of the insulating layer is removed to expose only a top portion of the first (second) gate structure. A portion of the insulating layer covering the first MOS transistor is removed to expose the first MOS transistor. Using the remaining insulating layer on the second MOS transistor as a mask, the Salicide fabrication process is performed to form a self-aligned silicide layer on the first interchangeable source/drain region, and the exposed top surface of the first (second) polysilicon gate structure.
REFERENCES:
patent: 5897348 (1999-04-01), Wu
patent: 5994176 (1999-11-01), Wu
patent: 6020240 (2000-02-01), Wu
patent: 6025267 (2000-02-01), Pey et al.
patent: 6025620 (2000-02-01), Kimura et al.
Chen Jacob
Chen Tung-Po
Lin Yung-Chang
Davis Jamie L.
Jr. Carl Whitehead
United Microelectronics Corp.
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