Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-03-25
2000-07-11
Booth, Richard
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438281, 438302, 438305, 438592, 438595, H01L2158234, H01L 21336, H01L 214763
Patent
active
060872276
ABSTRACT:
A method for fabricating an electrostatic discharge (ESD) protection circuit on a substrate is provided. The substrate includes an internal circuit region and an ESD protection region. A first MOS transistor is formed at the internal circuit region including a first gate structure, a first spacer, a first source/drain region with a first lightly doped drain (LDD) structure. A second MOS transistor is formed at the ESD protection circuit region including a second gate structure, a second spacer, a second source/drain region with a second LDD structure. The method includes forming a conformal metal layer over the substrate. A patterned photoresist layer is formed on the metal layer to expose a portion of the metal layer. Under the exposed portion of the metal layer it includes the second spacer and a portion of the second source/drain region. Using the patterned photoresist layer as a mask, the exposed portion of the metal layer and the spacer is removed so as to expose a portion of the second source/drain region. The patterned photoresist layer is still used as a mask for an ion implantation process. The ion implantation process is performed to smear the second LDD structure so as to form a third source/drain region that replaces the second source/drain region. The photoresist layer is removed. A thermal process is performed on the remaining metal layer to accordingly form a Salicide layer.
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Booth Richard
Pompey Ron
United Microelectronics Corp.
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