Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-08-21
1999-04-06
Brown, Peter Toby
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438305, 438289, 438290, 438291, 438525, 438766, H01L 218234
Patent
active
058917829
ABSTRACT:
A method of forming a MOS transistor without a lightly doped drain (LDD) region between the channel region and drain is provided. The channel region is formed from a tilted ion implantation after the deposition of the gate oxide layer. The tilted implantation forms a relatively short channel length, with respect to the length of the gate electrode. The position of the channel is offset, and directly adjoins the source. The non-channel area under the gate, adjacent the drain, replaces the LDD region between the channel and the drain. This drain extension acts to more evenly distribute electric fields so that large breakdown voltages are possible. The small channel length, and eliminated LDD region adjacent the source, act to reduce resistance between the source and drain. In this manner, larger I.sub.d currents and faster switching speeds are obtained. A MOS transistor having a short, offset channel and drain extension is also provided.
REFERENCES:
patent: 5403758 (1995-04-01), Yoshihara
patent: 5436175 (1995-07-01), Nakato et al.
patent: 5510279 (1996-04-01), Chien et al.
patent: 5648672 (1997-07-01), Hasegawa et al.
patent: 5767557 (1998-05-01), Kizilyalli
Article entitled, "A High Performance 0.1.mu.m MOSFET with Asymmetric Channel Profile" authored by Akira Hiroki, Shinji Odanaka, and Atsushi Hori, published in the 1995 IEEE, IEDM 95-439, pp. 17.7.1-17.7.4.
Article entitled, A New Asymmetrical Halo Source Gold Drain (HS-Gold) Deep Sub-Half-Micrometer n-MOSFET Design for Reliability and Performance, authored by Taqi N. Buti, Seiki Ogura, Nivo Rovedo and Kentaroh Tobimatsu, published in the IEEE Transactions on Electron Devices, vol. 38, No. 8, Aug. 1991, pp. 1757-1764.
Article entitled, "Potential Design and Transport Property of 0.1 .mu.m MOSFET with Asymmetric Channel Profile", authored by Shinji Odanaka and Akira Hiroki in the IEEE Transactions on Electron Devices, vol. 44, No. 4, Apr. 1997, pp. 595-600.
Hsu Sheng Teng
Lee Jong Jan
Brown Peter Toby
Maliszewski Gerald
Oh Edwin
Ripma David C.
Sharp Kabushiki Kaisha
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