Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-11-27
2002-04-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S619000
Reexamination Certificate
active
06380106
ABSTRACT:
BACKGROUND OF INVENTION
1)
Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of an inter metal dielectric (IMD) layers that have air gaps and most particularly to a metallization scheme using air gaps between metal lines and interconnects.
2)
Description of the Prior Art
The formation of air gaps between conducting lines of high speed Integrated Circuits (IC's) is typically a combination of the deposition of a metal layer, selective etching of the metal layer to form the desired line patterns, the deposition of a porous dielectric layer or a disposable liquid layer which is then selectively removed to form the desired air-gaps.
The continuing effort to reduce the size of individual transistors and other devices commonly integrated on a semiconductor chip and to increase the density of Integrated Circuits results in a continuing reduction of the separation between conducting layers of materials. This reduction results in an increase of capacitive crosstalk between adjacent conductor lines of a semiconductor circuit, that is the voltage on the first conductor line alters or affects the voltage on the second conductor line. This alteration in voltage can cause erroneous voltage levels in the Integrated Circuit making the IC increasingly prone to faulty operation. It becomes therefore imperative to reduce the resistive capacitance (RC) time constant and the crosstalk between adjacent conducting lines.
The capacitance between adjacent conducting lines is highly, dependent on the insulator or dielectric used to separate the conducting lines. Conventional semiconductor fabrication typically uses silicon dioxide as a dielectric, this has a dielectric constant of about 3.9.
The use of many of the low dielectric constant materials is not feasible due to the fact that equipment is not available to properly process the new dielectric materials in various integrated circuits. Also, the chemical or physical properties of many low dielectric constant materials are usually difficult to make compatible with or integrate into conventional integrated circuit processing.
The lowest possible and therefore the ideal dielectric constant is 1.0, this is the dielectric constant of a vacuum whereas air has a dielectric constant of less than 1.001
To reduce capacitive coupling and to reduce capacitive crosstalk, a major objective in the design of IC's is to reduce the Dielectric Constant (k) of the insulating layer between adjacent conductor lines of semiconductor circuits. The present invention makes a significant contribution within the scope of this effort.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 6,071,805(Liu) shows an air gap between lines. U.S. Pat. No. 6,071,830(Matsuzawa et al.) shows an air gap by an organic layer that expands when heated. U.S. Pat. No. 5,461,003(Havemann et al.) shows air gaps between metal lines formed by etching an organic filler through an oxide layer.
However, further improvements in air gap IMD metalization structures are needed.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a metallization scheme.
It is an object of the present invention to provide a method for fabricating a metallization scheme having air gaps between metal lines.
It is an object of the present invention to provide a method for fabricating a metallization scheme having an air gap formed by vaporizing a filler material through a permeable dielectric layer.
It is an object of the present invention to provide a method for fabricating a metallization structure having an air gap formed by vaporizing a filler material through a permeable dielectric layer using an insitu process.
To accomplish the above objectives, the present invention provides a method of manufacturing a metallization scheme with an air gap which is characterized as follows. Spaced conductive lines are formed over a semiconductor structure. The spaced conductive lines have top surfaces. A filler material is formed over the spaced conductive lines and the semiconductor structure. The filler material is preferably comprised of a low molecular weight organic polymer such as polypropylene glycol (PPG), polybutadine (PB) polyethylene glycol(PEG) and polycaprolactone diol (PCL) and is formed by a spin on process or CVD process. We etch back the filler material to expose the top surfaces of the spaced conductive lines. Next, the semiconductor structure is loaded into a HDPCVD chamber.
In a critical step, a permeable dielectric layer formed is over the filler material. The permeable dielectric layer has a property of allowing decomposed gas phase filler material to diffuse through. The permeable dielectric layer is thin enough to allow the vaporized/decomposed gas phase filler material to diffuse through.
In another critical step, we vaporize the filler material changing the filler material into a vapor phase filler material. The vapor phase filler material diffuses through the permeable dielectric layer to form a gap between the spaced conductive lines. The filler material vaporization is performed at a higher temperature than the deposition temperature of the permeable dielectric layer. Next, an insulating layer is deposited over the permeable dielectric layer. Now, we preferably remove the semiconductor structure from the HDPCVD chamber.
Important features of the present invention are the permeable dielectric layer that the filler layer diffuses through to create the air gap. The filler material is covered by the permeable dielectric layer and is not exposed to the atmosphere. This is a critical difference compared to the prior arts. Also, the permeable dielectric layer prevents the insulating layer from filling in the air gap. Also, the filler material is vaporized/decomposed by an insitu HPDCVD plasma process at an elevated temperature. Preferably the filler material is polybutadine (PB) or fluorinated amorphous carbon (a-FiC).
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.
REFERENCES:
patent: 5461003 (1995-10-01), Havemann et al.
patent: 6071805 (2000-06-01), Liu
patent: 6071830 (2000-06-01), Matsuzawa et al.
patent: 6141072 (2000-10-01), Drabik et al.
patent: 6150232 (2000-11-01), Chan et al.
patent: 6162838 (2000-12-01), Kohl
patent: 6165890 (2000-12-01), Kohl et al.
Ang Ting-Cheong
Lim Seng Keong Victor
See Alex
Siew Yong Kong
Teh Young-way
Chartered Semiconductor Manufacturing Inc.
Nelms David
Pike Rosemary L. S.
Saile George O.
Stoffell William J.
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