Method for fabricating a vertical transistor in a trench,...

Details Method for fabricating a vertical transistor in a trench,... Method for fabricating a vertical transistor in a trench,...

2007-04-24

2007-04-24

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S244000, C438S386000, C438S387000, C257SE21375

Reexamination Certificate

active

10484562

ABSTRACT:
To fabricate a vertical transistor, a trench is provided, the side wall of which is formed by a semiconductor substrate in single crystal form and the base of which is formed by a polycrystalline semiconductor substrate. A transition region is arranged between the side wall and the base. A semiconductor layer is deposited so that an epitaxial semiconductor layer grows on the side wall and a semiconductor layer grows on the base, with a space remaining between these layers. The semiconductor layers are covered with a thin dielectric, which partially limits a flow of current, and the space is filled. During a subsequent heat treatment, dopants diffuse out of the conductive material into the epitaxial semiconductor layer, where they form a doping region. The thin dielectric limits the diffusion of the dopants into the semiconductor substrate and prevents the propagation of crystal lattice defects into the epitaxial semiconductor layer.

REFERENCES:
patent: 5365097 (1994-11-01), Kenney
patent: 6093614 (2000-07-01), Gruening et al.
patent: 6144054 (2000-11-01), Agahi et al.
patent: 6262448 (2001-07-01), Enders et al.
patent: 6500707 (2002-12-01), Schrems
patent: 100 11 889 (2001-09-01), None
patent: 101 13 187 (2002-08-01), None
patent: 0 971 414 (2000-01-01), None
patent: WO 02/073657 (2002-09-01), None

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