Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-21
2001-10-16
Zarabian, Amir (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S548000, C438S923000, C438S561000
Reexamination Certificate
active
06303436
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention generally relates to a method of fabrication of a Mask ROM (Read Only Memory), and more precisely to a method of fabrication of a new type of Trench Mask ROM.
2. Background of the Related Art
As the complexity and performance of ICs increase, more processing steps are needed to fabricate them. Four or five mask levels were quite adequate for primitive ICs in the 1970s, whereas 16-Mb (ultra large-scale integration; ULSI) memory chips require more than twenty mask levels. For bit densities of up to one megabit, planar-type storage capacitors are used.
Read Only Memory is so named because its cells can read data only from the memory cells. The ROM can be distinguished as Mask ROM, PROM (Programmable ROM), EPROM (Erasable Programmable ROM) and EEPROM (Electrically Erasable Programmable ROM) due to what method a ROM uses to store data. The Mask ROM is the most fundamental ROM.
The fabrication of a typical planar type of Mask ROM is shown as follows. The description of the process sequence for forming a planar type of Mask ROM is as shown, in FIG
1
a
to FIG
1
e.
Referring to
FIG. 1
a,
a portion of the substrate
100
is lightly doped with a p-type dopant. Furthermore, there are field-oxide areas
106
on both sides of the top portion of the substrate
100
. A photo resist
104
is formed on the outer surface of the substrate
100
to define plural doped regions
102
. The plural doped regions
102
are formed using ion-implanting technique, wherein the plural doped regions
102
are implanted with n
+
-type ion, such as As or P. Photo resist
104
is removed. Photo resist
104
is used to define the doped regions
102
. Referring to
FIG. 1
b,
after removing the photo resist
104
, boron ions are implanted
107
into the substrate to form cell isolation region
108
. The cell isolation region
108
is used for suppressing the leakage. Referring to
FIG. 1
c,
a gate oxide layer
110
is formed on the substrate
100
and the doped regions
102
. And, a polysilicon layer
112
is formed sequentially on the gate oxide layer
110
. Referring to
FIG. 1
d,
a photo mask
114
is used during a boron ion-implanting step
119
, wherein the photo mask
114
is used to define a coding cell for forming a Mask ROM. Then, a Mask ROM is formed with some high-logic-level regions. As shown in FIG
1
e,
there is a fixed threshold voltage between two adjacent doped regions
102
. Accordingly, the doped regions
102
doped with n
+
-type dopant and the doped regions
116
doped with boron ions would increase the threshold voltage. Namely, a higher threshold voltage relates to a high-logic-level. Conversely, a low-logic-level is one pair of two of the adjacent doped regions
102
which contains an undoped region
118
between the two adjacent doped regions
102
.
However, as component density has increased, the amount of charge needed for a sufficient noise margin remains fixed. A device is composed of huge number of components. Further, a chip contains a lot of devices. The typical planar type of Mask ROM can't satisfy the reductions for the device scale. Hence, it is difficult to compose a huge number of devices on a small chip. Furthermore, as the size of device is reduced, the distance between two adjacent components is so close as to cause the current leakage on the surface of the device. Hence, the current leakage and small-scale integration lead the fabrication of the mask ROM to be restricted. Therefore, in order to reduce leakage and cell size, and form large-scale integration a new type of Trench Mask ROM cell is needed.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a new type of Trench Mask ROM cell and the fabricating method thereof. The Trench Mask ROM cell can achieve purposes such as forming a large-scale integration, reducing current leakage and the size of the device.
Briefly described, the present invention relates to a method for fabricating a Trench Mask ROM cell. An embodiment of the method comprises the steps as described as follows. First, a substrate lightly with p-type dopant is provided. A dielectric layer and a nitride layer are formed sequentially on the substrate. Plural trenches are formed using well-known etching techniques. After etching back the nitride layer and the oxide layer, the plural trenches are formed on the substrate. Then, a gate oxide layer is deposited on the surface of each trench. After the nitride layer is removed, n
+
-type ions are implanted into the top portion of the substrate between each trench, wherein the doped regions are beneath the pad oxide layer. These doped regions are used for being bit lines of the Mask ROM. The n
+
-type ions are arsenic or phosphorus ions. Further, a polysilicon layer is formed on the gate oxide layer. Finally, parts of trenches are implanted with n
+
-type ions for defining coding cells of a Trench Mask ROM by using a mask.
In another embodiment, the steps for forming plural trenches and implanting n
+
-type ions to form doped regions are reversed. These two methods can yield the same result for fabricating a Trench Mask ROM. By using these methods, the purposes of forming a large-scale integration, suppressing current leakage and reducing size of the device can be achieved.
REFERENCES:
patent: 5595927 (1997-01-01), Chen et al.
patent: 5998261 (1999-12-01), Hofmann et al.
patent: 6064101 (2000-05-01), Krautschneider et al.
patent: 6069058 (2000-05-01), Hong
Mosel Vitelic Inc.
Owens Beth E.
Zarabian Amir
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