Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-25
2001-10-30
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S188000, C438S192000, C438S202000, C438S211000, C438S270000, C438S268000
Reexamination Certificate
active
06309919
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to integrated circuits, and more particularly to a vertical complementary metal-oxide-semiconductor (CMOS) device and method for fabricating same.
BACKGROUND OF THE INVENTION
In traditional semiconductor fabrication techniques, integrated circuit devices such as transistors are laid out in a relatively planar, thin film at the surface of a semiconductor substrate. As time has passed, there has been a need to make these devices smaller and smaller, such that they occupy less “real estate” on the surface of the semiconductor chip which they occupy. As the dimensions of the device shrink, barriers to further downsizing begin to appear. For example, the depth of focus on small devices drops dramatically. One encounters line width control problems, alignment problems and problems with contacts. Squares become rounded in their shape; some features may disappear entirely with a loss of focus. Conventionally, the minimum size of a channel length of a transistor is determined by the minimum lithography obtainable by the stepper used to fabricate chips on the wafer. As the minimum channel length decreases, the cost of the stepper increases. A need therefore continues to exist for devices which occupy a small amount of real estate, whose critical dimensions are not controlled by lithographic constraints, and which at the same time have acceptable reliability, cost and operational performance.
SUMMARY OF THE INVENTION
The present invention relates to a device having a transistor channel formed to be approximately perpendicular to the surface of a substrate on which the device is formed. The length of this channel is therefore more independent of lithographic constraints. According to one aspect of the invention, a semiconductor layer is formed on the substrate to be of a first conductivity type. A heavily doped region is formed in the semiconductor layer to be spaced from the surface of the semiconductor layer and to be of a second conductivity type. A drain region is formed adjacent to the semiconductor layer surface and is spaced from an upper boundary of the heavily doped region by a channel region. A sidewall of the channel region extends from the top surface of the channel region at least to the boundary of the heavily doped region, and a gate insulator is formed on this sidewall. A conductive gate is formed adjacent the sidewall. A source voltage is connected to the heavily doped region. In this manner, a vertical channel region is formed between a drain region on the top of the device and a source region that is formed in the semiconductor layer. Preferably, the source voltage is supplied to the semiconductor layer through a source connector region that is formed to extend from the surface of the semiconductor layer to the boundary of the source region.
In one embodiment of the invention, the conductive gate, which for example can be highly doped polysilicon, is formed as a ring or other endless structure to surround that portion of the semiconductor layer that includes the channel region. The source connector region is formed laterally exterior to a trench containing the gate.
This device is preferably built as a mesa of semiconductor material on a substrate insulator (SOI); in a CMOS embodiment, a second device having reversed conductivity types for its components is built in another mesa. The mesas are separated from each other and from other devices by an insulator such as oxide.
Several technical advantages inhere in the device of the invention. There is no hot carrier injection concern, as the channel region conducts current in bulk in its body rather along its surface. The voltage distribution is more uniform. A higher performance is obtained because the horizontal area of the drain region is the same as the cross-sectional area of the channel region, making the effective transistor size larger. The channel length is not controlled by lithography, and thus a channel length of less than L can be obtained, where L is the minimum lithographic feature dimension. This channel region can instead be controlled by diffusion, implanting and etching. The device of the invention has much better reliability than conventional devices, as its voltage distribution is much better and there is no localized high electric field. The device is easier to scale and, because an advanced stepper is not needed, results in reduced manufacturizing costs.
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Liu Yowjuang W.
Wollesen Donald L.
Advanced Micro Devices , Inc.
Foley & Lardner
Rocchegiani Renzo N.
Smith Matthew
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