Method for fabricating a trench capacitor of DRAM

Details Method for fabricating a trench capacitor of DRAM Method for fabricating a trench capacitor of DRAM

2005-12-27

2005-12-27

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S246000, C438S248000, C438S386000, C438S389000, C438S391000

Reexamination Certificate

active

06979613

ABSTRACT:
A method for fabricating a deep trench capacitor. A substrate is provided having a pad oxide layer and a pad nitride layer stacked on a main surface thereof. A deep trench is etched into the substrate through the pad oxide layer and the pad nitride layer. A node dielectric is coated on the interior surface of the deep trench. A silicon spacer layer is formed on the sidewall of the deep trench over the node dielectric. An upper portion of the silicon spacer layer is doped with dopants such as BF2. The undoped portion of the silicon spacer layer is selectively removed to expose a portion of the node dielectric. The exposed node dielectric is stripped off to expose the substrate. The remaining node dielectric covered by the doped silicon spacer layer forms a protection spacer for protecting the pad oxide layer from corrosion during the subsequent etching processes.

REFERENCES:
patent: 5360758 (1994-11-01), Bronner et al.
patent: 5614431 (1997-03-01), DeBrosse
patent: 6916721 (2005-07-01), Heineck et al.
patent: 6930004 (2005-08-01), Wang et al.
patent: 2005/0106831 (2005-05-01), Hsu et al.

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