Method for fabricating a sub-half micron MOSFET device with glob

Details Method for fabricating a sub-half micron MOSFET device with glob Method for fabricating a sub-half micron MOSFET device with glob

1996-09-03

1998-01-20

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438427, H01L 21336

Patent

active

057100764

ABSTRACT:
A process for globally planarizing the insulator used to fill narrow and wide shallow trenches, used in a MOSFET device, structure, has been developed. The process features smoothing the topography that exists after the insulator filling of narrow and shallow trenches, via use of a two layer planarization composite, consisting of an underlying, anti-reflective coating, which enhances the flow of an overlying photoresist layer. A two phase, RIE procedure is then employed, with the initial phase exposing thick insulator in narrow shallow trench regions, but leaving the two layer planarization composite protecting the thinner insulator in the wide shallow trenches. The second phase of the RIE procedure removes thick insulator, overlying the narrow shallow trenches, resulting in a planarized topography.

REFERENCES:
patent: 4927777 (1990-05-01), Hsu et al.
patent: 5077234 (1991-12-01), Scoopo et al.
patent: 5362669 (1994-11-01), Boyd et al.
patent: 5428240 (1995-06-01), Lur
"Effect of Circuit Structure on Planarization Resist Thickness" by R.H. Wilson et al, pubin J. Electrochem Soc. Solid-State Science And Technology, May 1986 pp. 981-984.
"Two Layer Planarization Process" by A. Schlitz et al, pubin J. Electrochem Soc. Solid-State Science And Technology, Jan. 1986, pp. 178-181.
"Application Of A Two-Layer Planarization Process To VLSI Intermetal Dielectric And Trench Isolation Processes", pub in IEEE Trans on Semi Manufacturing, vol. 1, No. 4, Nov. 1988 pp. 140-145.
"Planarization of VLSI Topography Over Variable Pattern Densities" by T.H. Daubenspeck et al., pub in J. Electrochem Soc. vol. 138, Feb. 1991, pp. 506-509.

Affiliated with

Also associated with

Rating

Method for fabricating a sub-half micron MOSFET device with glob does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating a sub-half micron MOSFET device with glob, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a sub-half micron MOSFET device with glob will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-725007