Method for fabricating a split gate flash memory cell

Details Method for fabricating a split gate flash memory cell Method for fabricating a split gate flash memory cell

2003-04-30

2004-03-30

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S211000, C438S267000, C438S596000

Reexamination Certificate

active

06713349

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a split gate flash memory cell to increase the integration of integrated circuits (ICs).
2. Description of the Related Art
Non-volatile memory, such as flash memory, stores data regardless of electrical power supplied, and reads and writes data by controlling a threshold voltage of a control gate. Conventionally, flash memory includes a floating gate and a control gate. The floating gate stores charge and the control gate reads and writes data. In addition, the floating gate is located under the control gate and is not connected to external circuit, and the control gate connects to the word line. One of the advantages of flash memory is its capacity for block-by-block memory erasure. Furthermore, the speed of memory erasure is fast, and normally takes just 1 to 2 seconds for the complete removal of a whole block of memory. Therefore, in recent years, it is widely applied for consumer electronics devices, such as digital cameras, mobile phones, personal stereos, and laptops.
FIG. 1
is a cross-section showing a conventional split gate flash memory cell. The memory cell includes a silicon substrate
100
having a source region S and a drain region D. A source line
110
is disposed on the source region S. A floating gate
104
and silicon oxide layers
102
,
106
are disposed over the substrate
100
outside the source line
110
, and the floating gate
104
is insulated from the source line
110
by a spacer
108
. A control gate
114
with an “arc” profile formed by spacer method is disposed over the substrate
100
outside the floating gate
104
and insulated by a silicon oxide layer
113
. In addition, the bit line
120
disposed in the contact hole
119
is insulated from the control gate (word line)
114
by the interlayer dielectric (ILD)
118
and the spacer
116
.
However, in such a flash memory cell, it is difficult to control the thickness of the control gate
114
with an “arc” profile. That is, the critical dimension (CD) of the control gate
114
cannot be precisely controlled. Moreover, since an interval L between the bit line
120
and the control gate
114
must prevent the failure due to circuit short, the line width of the bit line
120
is limited. As a result, the integration of integrated circuits is limited and the device is more difficult to fabricate when the size of device is reduced.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide a novel method for fabricating a split gate flash memory cell to increase the integration of ICs by decreasing the interval between the word line and the bit line.
Another object of the invention is to provide a novel method for fabricating a split gate flash memory cell to precisely control the critical dimension (CD) of the control gate and reduce its resistance.
According to one aspect, the invention provides a method for fabricating a split gate flash memory cell. First, a substrate having a doped region and a first conductive layer formed thereover is provided. Next, a floating gate and a first insulating layer are successively formed over the substrate on both sides of the first conductive layer, wherein the floating gate is insulated from the first conductive layer and the substrate. Next, a conformable second insulating layer and a conformable second conductive layer are successively formed on the substrate and the first insulating layer, and a third insulating layer is then formed thereon. Next, the third insulating layer is etched back to expose the second conductive layer. Subsequently, the exposed second conductive layer is etched back to expose the second insulating layer. Next, a cap layer is formed on the exposed second conductive layer. Thereafter, the third insulating layer is removed to form an opening and expose the second conductive layer. Next, the second conductive layer under the opening is removed to expose the second insulating layer and form a control gate composed of the remaining second conductive layer underlying the cap layer. Next, the second insulating layer under the opening is removed to expose the substrate and form a contact hole. Finally, a metal layer is formed in the contact hole and insulated from the control gate.
Moreover, the profile of the control gate is rectangular. In addition, the metal layer serves as a bit line and the first conductive layer serves as a source line.
According to another aspect., the invention provides a method for fabricating a vertical split gate flash memory cell. First, a substrate having a doped region and a first conductive layer formed over the doped region is provided. Next, a floating gate and a first insulating layer are successively formed over the substrate on both sides of the first conductive layer, wherein the floating gate is insulated from the first conductive layer and the substrate. Next, a conformable second insulating layer, a conformable second conductive layer, and a conformable third conductive layer are successively formed on the substrate and the first insulating layer, and then a third insulating layer is formed thereon. Next, the third insulating layer is etched back to expose the third conductive layer. Subsequently, the exposed third and second conductive layers are etched back to expose the second insulating layer. Next, a cap layer is formed on the exposed third and second conductive layers. Thereafter, the third insulating layer is removed to form an opening and expose the third conductive layer. Next, the third and second conductive layers under the opening are removed to expose the second insulating layer and form a control gate composed of the remaining second conductive layer underlying the cap layer. Next, the second insulating layer under the opening is removed to expose the substrate and form a contact hole. Finally, a metal layer is formed in the contact hole and insulated from the control gate.
Moreover, the profile of the control gate is rectangular. In addition, the metal layer serves as a bit line and the first conductive layer serves as a source line.


REFERENCES:
patent: 5891775 (1999-04-01), Hisamune
patent: 6096603 (2000-08-01), Chang et al.
patent: 6180461 (2001-01-01), Ogura
patent: 6436764 (2002-08-01), Hsieh
patent: 6482700 (2002-11-01), Chen et al.
patent: 6525371 (2003-02-01), Johnson et al.
patent: 6562673 (2003-05-01), Lin
patent: 6589842 (2003-07-01), Huang

Affiliated with

Also associated with

Rating

Method for fabricating a split gate flash memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating a split gate flash memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a split gate flash memory cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3217733