Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-07-08
2003-11-04
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000
Reexamination Certificate
active
06642116
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device, and more particularly to the fabrication of a split gate memory cell of a flash memory.
2. Description of the Prior Art
Complementary metal-oxide-semiconductor (CMOS) memory can be divided into two main categories: random access memory (RAM) and read-only memory (ROM). ROM's market share has been continuously growing in the past few years, and further growth in the near future is foreseen, especially for flash memory in which a single cell can be electrically programmable and a block, sector or page of cells that are electrically erasable at the same time. Due to the flexibility of flash memory against electrically programmable read-only memory (EPROM), electrically programmable but erasable via ultraviolet exposure, the market share of flash memory is also experiencing rapid growth. Electrically erasable and programmable read-only memory (EEPROM), electrically erasable and programmable per single byte, will be manufactured for specific applications only, since they use larger area and are more expensive. In recent years, flash memory has found interesting applications in electrical consumer products such as: digital cameras, digital video cameras, cellular phones, laptop computers, mobile MP3 players, and Personal Digital Assistants (PDA's). Since portability of these electrical consumer products is strongly prioritized by consumers, the products' size must be minimal. As a result, the capacity of the flash memory must be enlarged, and functions have to be maximized while size is reduced. The capacity of flash memory has increased from 4 to 256 MB, and will increase to even 1 GB in the near future. With the increase in packing density for flash memory, floating gates and control gates have to be made as small as possible. In conventional processes, masks are usually used to define the gates in flash memory.
FIGS. 1A
to
1
G show the manufacturing processes of a conventional split gate flash memory device.
As shown in
FIG. 1A
, a semiconductor substrate
100
is provided. An LOCOS Oxidation process is performed to form a field insulating layer (not shown) on the substrate
100
. The field insulating layer isolates each active area. A first insulating layer
110
is formed on the substrate
100
within the active area. The first insulating layer
110
can be made of oxide formed by oxidation and has a thickness of from 50 to 200 angstroms. Then, a first conductive layer
115
, which has a thickness of about 100 to 2000 angstroms, is formed on the first insulating layer
110
. The first conductive layer
115
is usually made of doped polycrystalline silicon formed by chemical vapor deposition (CVD) process. Then, a first masking layer
120
, with a thickness of about 500 to 2000 angstroms, is formed on the first conductive layer
115
by depositing a silicon nitride layer.
As shown in
FIG. 1B
, a portion of the first masking layer
120
is removed by performing photolithography and etching process to define the first opening
125
and to expose the surface of the first conductive layer
115
.
As shown in
FIG. 1C
, a floating gate insulating layer
130
is formed on the exposed surface of the first conductive layer
115
by an oxidation process.
After oxidation, as shown in
FIG. 1D
, the first masking layer
120
is removed by performing an etching process. Then, using the floating gate insulating layer
130
as a hard mask, a portion of the first conductive layer
115
and the first insulating layer
110
are sequentially removed to expose the surface of the substrate
100
by an etching process. The portions of the first conductive layer
115
and the first insulating layer
110
under the floating gate insulating layer
130
remain. The remaining first conductive layer
115
forms a floating gate
136
. The remaining first insulating layer
110
will be expressed as a first gate insulating layer
112
. Conductive tips
138
situated at the edge of the floating gate
136
are used for tip discharging when flash memory is erasing. Then, a second insulating layer
132
is formed on the surface of the substrate
100
, the oxide layer
130
, the floating gate
136
and the first gate insulating layer
112
. The second insulating layer
132
, which has a thickness of about 50 to 250 angstroms, is an oxide and is formed by oxidation or CVD.
As shown in
FIG. 1E
, a second conductive layer
135
is formed on the second insulating layer
132
. The second conductive layer
135
has a thickness of about 1000 to 2000 angstroms and is usually made of the doped polycrystalline silicon formed by CVD.
As shown in
FIG. 1F
, portions of the second conductive layer
135
and the second insulating layer
132
are removed by photolithography and etching to form a second opening
142
and a third opening
144
. The remaining second conductive layer
135
forms the control gate
170
. The remaining second insulating layer
132
will be expressed as a second gate insulating layer
155
.
As shown in
FIG. 1G
, a source region
180
is formed on the exposed substrate
100
by implanting N-type ions, such as phosphorus or arsenic into the substrate
100
, which is exposed in the second opening
142
. Then, an oxide layer (not shown) is formed to cover the surface and the sidewalls of the control gate
170
, the surface of the floating gate insulating layer
130
, the sidewalls of the second gate insulating layer
155
, floating gate
136
, and the first gate insulating layer
112
. Etching is performed to remove portions of the oxide layer and form the sidewall spacers
150
on the sidewalls of the floating gate
136
, the first gate insulating layer
112
, the control gate
170
and the second gate insulating layer
155
. A drain region
190
is formed on the exposed substrate
100
by implanting N-type ions, such as phosphorus or arsenic into the substrate
100
, which is exposed in the third opening
144
. The manufacture of a cell of flash memory is thus completed.
The conventional processes for fabricating flash memory usually form a floating gate insulating layer by thermal oxidation on a doped polycrystalline silicon, then use the floating gate insulating layer as a hard mask to etch portions of doped polycrystalline silicon uncovered by the floating gate insulating layer, such that the floating gate is formed. As memory devices become more integrated, the minimization of feature size of flash memory is needed. The sharpness of the floating gate has been limited due to the gate insulating layer formed by oxidizing. Thus, the minimization of the feature size can not be achieved.
SUMMARY OF THE INVENTION
An object according to the present invention is to provide a method of fabricating a split gate flash memory cell with improved feature of the floating gate characterized by minimization of the feature size.
The present invention achieves the above-indicated object by forming a buffer layer on a conductive layer as a floating gate insulating layer. Next, conductive spacers are formed on the sidewalls of the floating gate insulating layer. Then, the residual conductive layer and the conductive spacers are combined as a floating gate. The process for forming the floating gate insulating layer of the present invention is easily controlled. The tips of the conductive spacers are conductive tips. The matured etching process is used to form the conductive spacers, such that the conductive tips of the present invention can be sharper than those of the prior art. Therefore, minimization of the feature size can be achieved.
A method of fabricating a split gate flash memory cell first provides a semiconductor substrate. Defining an active area on the substrate, a first insulating layer is formed within the active area. A first conductive layer is formed on the first insulating layer. Then, a buffer layer is formed on the first conductive layer. Portions of the buffer layer are removed to form a floating gate insulating layer. A second conductive layer is formed on the surface of the
Elms Richard
Merchant & Gould P.C.
Nanya Technology Corporation
Owens Beth E.
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