Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-04-30
2003-11-18
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S595000
Reexamination Certificate
active
06649474
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a method for fabricating a semiconductor device. More particularly, it relates to a method for fabricating a source line of a flash memory cell that increases its top area.
2. Description of the Related Art
Non-volatile memory, such as flash memory, stores data regardless of electrical power supplied, and reads and writes data by controlling a threshold voltage of a control gate. Conventionally, flash memory includes a floating gate and a control gate. The floating gate stores charge and the control gate reads and writes data. In addition, the floating gate is located under the control gate and is not connected to external circuit, while the control gate connects to the word line. One of the advantages of flash memory is its capacity for block-by-block memory erasure. Furthermore, memory erasure is fast, and normally takes just 1 to 2 seconds for the complete removal of a whole block of memory. Therefore, in recent years, it has been widely applied to consumer electronics devices, such as digital cameras, mobile phones, personal stereos, and laptops.
FIG. 1
is a cross-section showing a conventional flash memory cell structure. The memory cell includes a silicon substrate
100
having a source region S therein. A source line
110
is disposed on the source region S. A floating gate
104
and silicon oxide layer
106
are disposed over the outside source line
110
. Moreover, the floating gate
104
is insulated from the substrate
100
by a silicon oxide layer
102
and insulated from the source line
110
by a spacer
108
. A control gate
114
, such as a conductive spacer, is disposed over the outside floating gate
104
and insulated therefrom by silicon oxide layer
113
.
In this flash memory cell structure, in order to reduce the resistance of the control gate
114
and source line
110
, a thin metal silicide (not shown) layer, such as titanium silicide (TiSi), is usually formed on the top surface. With the size of individual semiconductor devices reduced to increase density on the integrated circuit (IC) chip, the source line
110
width must be reduced to achieve a memory cell with a minimum size. However, when the source line
110
width is less than 0.2 &mgr;m, a titanium silicide layer cannot be formed on the source line
110
successfully and requires use of cobalt silicide (CoSi). Accordingly, the manufacturing cost is increased due to changed processing apparatus for forming cobalt silicide layer. Otherwise, the integration of IC is reduced since the size of devices cannot be.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide a novel method for fabricating a source line of a flash memory cell to form a source line having a “T” profile, thereby increasing its top area.
Another object of the invention is to provide a novel method for fabricating a source line of a flash memory cell to reduce the resistance of the source line still by titanium silicide when the size of the device is shrunk.
According to one aspect, the invention provides a method for fabricating a source line of a flash memory cell. First, a substrate covered by a first insulating layer, a first conductive layer, and a second insulating layer successively is provided. Next, the second insulating layer is patterned to form an opening over the substrate and expose the first conductive layer. Next, a first spacer is formed over the sidewall of the lower opening and a second spacer is formed over the sidewall of the upper opening and the first spacer. Next, the exposed first conductive layer under the opening is removed, and a third spacer over the sidewall of the first spacer and the second spacer is formed. Finally, the opening is filled with a second conductive layer to serve as a source line. Moreover, the method further comprises a step of forming a source region in the substrate under the opening, connected to the second conductive layer.
Moreover, the first insulating layer is silicon oxide and the second insulating layer is silicon nitride. The first and second conductive layers are polysilicon. The first, second, and third spacers are silicon oxide.
REFERENCES:
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5631179 (1997-05-01), Sung et al.
patent: 5686332 (1997-11-01), Hong
patent: 5756385 (1998-05-01), Yuan et al.
patent: 6218246 (2001-04-01), Kwon
patent: 6232179 (2001-05-01), Sato
patent: 6265265 (2001-07-01), Lim
patent: 2002/0142545 (2002-10-01), Lin
Huang Chung-Lin
Lin Chi-Hui
Booth Richard
Nanya Technology Corporation
Quintero Nelson A.
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