Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-07-12
2005-07-12
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S258000, C438S664000
Reexamination Certificate
active
06916701
ABSTRACT:
Disclosed is a method for fabricating a silicide layer of a flat cell memory device. The disclosed method comprises the steps of: providing a silicon substrate whereon a flat cell array region and a peripheral circuit region are defined; forming a word line and a bit diffusion layer on the flat cell array region of the substrate and a word line and source/drain junction on the peripheral circuit region; forming a gap fill insulating layer to fill up the gap between the word lines; removing the gap fill insulating layer on the peripheral circuit region; forming an insulating layer on the whole substrate; dry etching the insulating layer to expose a surface of word line, and a surface of the substrate of the peripheral circuit region, thereby forming a spacer on a side wall of the word line of the peripheral circuit region; and forming a silicide layer on the upper part of the word line of the flat cell array region and, at the same time, forming a salicide layer on the upper part of the word line and the surface of the substrate of the peripheral circuit region.
REFERENCES:
patent: 6146994 (2000-11-01), Hwang
patent: 6162675 (2000-12-01), Hwang et al.
patent: 6413861 (2002-07-01), Huang et al.
patent: 6448130 (2002-09-01), Kim
patent: 6468867 (2002-10-01), Lai et al.
DongbuAnam Semiconductor Inc.
Fourson George
Keefer Timothy J.
Seyfarth Shaw LLP
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