Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-07-31
2007-07-31
Estrada, Michelle (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S386000, C438S700000, C438S944000, C257SE27091, C257SE21651, C257SE27092, C257SE29346
Reexamination Certificate
active
11154943
ABSTRACT:
The present invention provides a method for fabricating a shadow mask in a trench of a microelectronic or micromechanical structure, comprising the steps of: providing a trench in the microelectronic or micromechanical structure; providing a partial filling in the trench; providing a first liner mask layer on the partial filling; providing a sacrificial filling on the liner mask layer to completely fill the trench; shallow etching back of the sacrificial filling into the trench; forming a first mask on the top side of the sacrificial filling in the trench; removing a subregion of the sacrificial filling in the trench using the first mask; and optionally removing a subregion of the first liner mask layer below it on the partial filling, the remaining subregion of the sacrificial filling in the trench serving as a second mask.
REFERENCES:
patent: 2002/0090824 (2002-07-01), Jaiprakash et al.
patent: 2003/0003652 (2003-01-01), Gobel et al.
patent: 2005/0009268 (2005-01-01), Cheng et al.
patent: 2005/0277264 (2005-12-01), Cheng et al.
Regul Jörn
Temmler Dietmar
Eschweiler & Associates LLC
Estrada Michelle
Infineon - Technologies AG
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