Method for fabricating a semiconductor transistor and structure

Details Method for fabricating a semiconductor transistor and structure Method for fabricating a semiconductor transistor and structure

1991-04-15

1994-01-11

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257336, 257338, 257346, 257387, 257408, 257900, 437 34, 437 41, 437 57, 437913, 437984, H01L 2702, H01L 21265

Patent

active

052784410

ABSTRACT:
A method for fabricating a CMOS field effect transistor with LDD (light doped drain) structure is disclosed. A first gate for an NMOS transistor and a second gate for a PMOS transistor are formed on a semiconductor substrate, and the NMOS and PMOS transistor regions are subjected to different ion implantation processes so as to form a first source and drain of low concentration. After forming a first spacer on the side walls of the gates, the substrate is subjected to another ion implantation so as to form a second source and drain of high concentration for the NMOS transistor. After forming a second spacer on the side surfaces of the first spacers, the substrate is subjected to still another ion implantation so as to form a second source and drain of high concentration for the PMOS transistor. Then is obtained a CMOS transistor provided with a PMOS transistor of LDD structure without increasing the diffusion resistance of an NMOS transistor.

REFERENCES:
patent: 4949136 (1990-08-01), Jain
patent: 4985744 (1991-01-01), Spratt et al.
patent: 5021353 (1991-06-01), Lowry et al.
patent: 5091763 (1992-02-01), Sanchez

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