Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2007-01-22
2010-02-16
Nguyen, Khiem D (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S455000, C257SE21511
Reexamination Certificate
active
07662665
ABSTRACT:
A method for fabricating a semiconductor package is provided. In one embodiment, a semiconductor chip having a plurality of exposed conductive layers thereon is provided. A first substrate having a first surface and a second surface is provided, the first surface having a plurality of exposed via plugs thereunder. The semiconductor chip is bonded to the first substrate, wherein the plurality of exposed conductor layers are aligned and in contact with the surfaces of the exposed via plugs. A portion of the second surface of the first substrate is then removed to expose the opposite ends of the plurality of via plugs. A plurality of UBM layers is formed on the surfaces of the opposite ends of the plurality of via plugs. A plurality of solder bumps is formed and mounted on the UBM layers. A second substrate having a first surface and a second surface is provided, the solder bumps being mounted to the first surface of the second substrate. A plurality of solder balls is formed and mounted to the second surface of the second substrate. A third substrate is mounted to the solder balls.
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patent: 6081429 (2000-06-01), Barrett
patent: 6943442 (2005-09-01), Sunohara et al.
patent: 6982380 (2006-01-01), Hoffmann et al.
patent: 7235889 (2007-06-01), Othieno et al.
patent: 2003/0168256 (2003-09-01), Chien
Chang Kuo-Chin
Chen Chen-Shien
Lii Mirng-Ji
Lu Szu-Wei
Tsao Pei-Haw
Birch & Stewart Kolasch & Birch, LLP
Nguyen Khiem D
Taiwan Semiconductor Manufacturing Co. Ltd.
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