Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-07-01
2004-11-16
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S399000, C438S672000
Reexamination Certificate
active
06818503
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for fabricating a semiconductor memory device.
In modern semiconductor memory devices, in particular in FeRAMs (Ferro-Electric Random Access Memories) or other memory devices, a semiconductor substrate or the like, a passivation region and/or a surface region thereof are formed with a CMOS (Complementary Metal Oxide Semiconductor) structure. Furthermore, a capacitor configuration including a plurality of capacitor devices serving as storage elements is provided in the region of the semiconductor substrate, in a passivation region and/or in a portion thereof. First and second contact regions or plug regions are formed for contacting the capacitor devices of the capacitor configurations to the CMOS structure.
An objective of the ongoing development of modern semiconductor memory technologies is, inter alia, the formation of the highest and most extensive integration density possible. Furthermore, it is a further objective to configure fabrication methods in a manner that is as simple and operationally economically expedient as possible.
What is problematic in the case of existing fabrication methods is that a plurality of the components provided in modern semiconductor memory devices can be produced and patterned only in the context of separate work steps that are to be performed one after the other. This applies in particular to the plurality of different contact regions or plug regions and the contact connection thereof to the storage capacitors, on the one hand, and to the underlying CMOS structure, on the other hand.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a semiconductor memory device which overcomes the above-mentioned disadvantages of the heretofore-known methods of this general type and which can be performed in a simple manner and in which, in particular, different process steps can be performed jointly whilst at the same time ensuring the functional reliability of the components.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a semiconductor memory device, the method includes the steps of:
forming a CMOS structure in a semiconductor substrate region and/or a passivation region and/or a surface region of the semiconductor substrate region and/or a surface region of the passivation region;
forming a capacitor configuration in the semiconductor substrate region and/or the passivation region and/or the surface region of the semiconductor substrate region and/or the surface region of the passivation region such that the capacitor configuration includes a plurality of capacitor devices serving as storage elements;
providing at least first and second contact regions for contacting the capacitor devices to the CMOS structure;
forming a first electrode device as a bottom electrode device, a second electrode device as a top electrode device and a dielectric between the first electrode device and the second electrode device for each of the capacitor devices; and
forming at least some of the first and second contact regions with respective elevated regions in the passivation region such that the elevated regions are elevated above the surface region of the passivation region.
In other words, a method for fabricating a semiconductor memory device is provided, in which a semiconductor substrate, a passivation region and/or a surface region thereof are formed with a CMOS structure; in which a capacitor configuration of a plurality of capacitor devices serving as storage elements is formed in the region of the semiconductor substrate, the passivation region and/or the surface region thereof; in which at least first and second contact regions or plug regions are provided for the contact connection of the capacitor devices to the CMOS structure; in which a first, bottom electrode device, a second, top electrode device and a dielectric formed in each case between the electrode devices are provided for each of the capacitor devices, and in which at least some of the first and/or second contact regions or plug regions, in the passivation region, are formed with a region in each case elevated above the surface region of the passivation region.
The method for fabricating a semiconductor memory device according to the invention is distinguished by virtue of the fact that at least some of the first and/or second contact regions or plug regions, in the first passivation region, are formed with a region in each case elevated above the surface region of the passivation region.
It is thus a basic idea of the present invention, in a fabrication method for semiconductor memory devices, to form the various plug regions or contact regions that are to be provided, for the contact connection of storage capacitors to the underlying CMOS structure, with elevated structures which extend beyond the surface region of a passivation region on the semiconductor substrate. In this way, a plurality of required contact connections with the contact regions or plug regions can be formed more simply because, for example, contacts that are to be incorporated into the depth of the passivation region to the plug regions and the processing thereof can be realized more simply, especially as the plug regions virtually extend in the direction toward the storage capacitors that are to be provided.
In accordance with a particularly preferred embodiment of the method according to the invention for fabricating a semiconductor memory device, it is provided that the first and second contact regions or plug regions that are to be provided are formed essentially together, in particular in a common process step, in a common and/or cascaded process sequence or the like. What is thereby achieved in an advantageous manner compared with the prior art is that the entire process sequence is carried out in a simplified manner in respect of production technology and in a shortened time.
It is thus a basic idea of the embodiment according to the invention to combine the formation of the various plug regions or contact regions that are to be provided, for contact connection of the storage capacitors to the rest of the semiconductor memory device, in particular to the underlying CMOS structure, in a single step, in a common process sequence or in a common cascaded process section, so that they are thus formed essentially simultaneously.
In this case, in an advantageous manner, it is provided, in particular, that the contact regions or plug regions are formed and patterned after the formation of the passivation region. This ensures that the possibly sensitive underlying semiconductor circuit for the semiconductor memory device, namely the CMOS structure, once it has been produced, can be processed further in a protected manner without being further influenced.
It is furthermore preferred that the elevated regions of the first and/or second contact regions or plug regions are formed by at least partial and/or selective masking and/or etching back of the first passivation region provided with the first and/or second contact regions or plug regions and/or of the first and/or second contact regions or plug regions.
Thus, in accordance with this embodiment, firstly either the totality of the contact regions or plug regions is introduced into the existing passivation region by the formation of cutouts and subsequent filling. Or, alternatively, firstly the contact regions or plug regions are constructed at predetermined positions and are then subsequently embedded In a corresponding passivation region. In any event, however, the total configuration including passivation region and contact regions or plug regions formed therein is patterned by a corresponding etching-back operation in conjunction with a lithographic step, corresponding masks being formed on free surfaces according to the fundamental structure desired, so that the corresponding removal of material is effected only at the unprotected surface regions. It is thus po
Bruchhaus Rainer
Enders Gerhard
Hartner Walter
Kasko Igor
Krönke Matthias
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Perkins Pamela E
Stemer Werner H.
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