Method for fabricating a semiconductor memory device

Details Method for fabricating a semiconductor memory device Method for fabricating a semiconductor memory device

1999-10-22

2001-09-18

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S003000, C438S240000, C438S256000

Reexamination Certificate

active

06291292

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a method for fabricating a semiconductor memory device, and more particularly to a semiconductor memory device and a method for fabricating the same where a ferroelectric film, a high dielectric film or pyroelectric film is used as a capacitor.
BACKGROUND OF THE INVENTION
In general, a ferroelectric random access memory(FeRAM) device is nonvolatile and the data stored in the FeRAM device are not removed in power off. However, if the thickness of the capacitor is very thin, switching polarization is occurred fast so that the FeRAM device is able to read out the data therefrom or write the data therein with high speed and low voltage. The FeRAM device may constitute memory cells in which each memory cell is comprised of a transistor and a ferroelectric capacitor so that it is applicable to semiconductor memory device with high density. There are typically SrBi
2
Ta
2
O
9
(SBT), Pb(ZrTi)O
3
(PZT) as ferroelectric films, (Ba,Sr)TiO
3
as a dielectric film, and PbTiO
3
and (Pb,La)TiO
3
as pyroelectric films respectively.
FIG.1
is a cross-sectional view for illustrating a method for fabricating the semiconductor memory device.
Referring to
FIG. 1
, in order to define an active region, a field oxide layer
11
is formed on a selected portion of a semiconductor substrate
10
. A gate insulating layer
12
and a conductive layer
13
for gate electrode are successively deposited at the active region of the semiconductor substrate
10
. Selected portions of the conductive layer
13
for gate electrode and the gate insulating layer
12
are patterned thereby forming a gate electrode
14
. Impurities are ion-implanted to both sides of the gate electrode
14
, thereby forming source and drain regions
15
a,
15
b.
Then, a transistor is completed. A first intermetal insulating layer
16
is deposited on the semiconductor substrate
10
in which the transistor is formed, and the first intermetal insulating layer
16
is etched to expose the drain region
15
b
thereby forming a contact hole within the first intermetal insulating layer
16
. So as to contact with the exposed drain region
15
b,
a bit line
17
is formed within the contact hole and on the first intermetal insulating layer
16
. A second intermetal insulating layer
18
is formed on the first intermetal insulating layer
16
in which the bit line
17
is formed. The second intermetal insulating layer
18
and the first intermetal insulating layer
16
are etched to expose the source region
15
a
of the transistor thereby forming a contact hole. Next, a plug
19
is formed such that the contact hole is buried. The plug
19
is formed of polysilicon material. A glue layer
20
, a metal film
21
for lower electrode, a dielectric layer
22
and a metal film
23
for upper electrode are successively deposited on the plug
19
and the second intermetal insulating layer
18
. The metal film
23
for upper electrode, the dielectric layer
22
, the metal film
21
for lower electrode and the glue layer
20
are patterned to contact with the plug
19
thereby forming a capacitor
24
. The dielectric layer
22
can be formed of ferroelectric film, high dielectric film or pyroelectric film.
However, since the plug
19
connecting the source region
15
a
and the capacitor
24
is made of polysilicon, layers formed on the plug
19
, i.e. the glue layer
20
, the metal film
21
for lower electrode, the dielectric layer and the metal film
23
for upper electrode have polycrystalline structures. Thus, volatile components i.e. Pb, Bi, O in the dielectric layer
22
, are diffused to the metal film
21
for lower electrode and the glue layer
20
through a grain boundary of the dielectric layer
22
and the metal film
21
for lower electrode. Thus, characteristics of the metal film
21
for lower electrode and the glue layer
20
are degraded. Since, the volatile components of the dielectric layer
22
are diffused, dielectric characteristic of dielectric layer is degraded.
SUMMARY OF THE INVENTION
Accordingly, it is the object of the present invention to prevent volatile components in the dielectric layer from being diffused into the lower electrode and the glue layer.
It is yet another object of the present invention to secure high dielectric characteristic of dielectric layer in capactor.
To accomplish the object of the present invention in one aspect, the present invention provides a semicondudctor memory device comprising: a single crystalline silicon substrate; a transistor formed at a selected portion of the single crystalline substrate, wherein the transistor comprises a gate electrode, a source region and a drain region; a plug electrically contacted with the source region and formed of a single crystalline epitaxial layer; a lower electrode formed of the single crystalline epitaxial layer contacted to the plug; a dielectric layer formed over the lower electrode and formed of the single crystalline epitaxial layer; and an upper electrode formed over the dielectric layer and formed of the single crystalline epitaxial layer, wherein the dielectric layer is formed of a layer selected among ferroelectric layer, high dielectric layer or pyroelectric layer.
In another aspect, the present invention provides a method for fabricating a semiconductor memory device comprising the steps of: forming source and drain regions at selected portions of a semiconductor substrate in which an active region is defined; forming a plug contacted with the source region by growing the semiconductor substrate according to an epitaxial method; forming a gate electrode between the source and the drain regions; forming a first intermetal insulating layer on the semiconductor substrate; forming a bit line contacted with the drain region by penetrating the first intermetal insulating layer; forming a second intermetal insulating layer on the first intermetal insulating layer in which the bit line is formed; removing the first and the second intermetal insulating layers so as to expose a surface of the plug; growing a glue layer and a conductive layer for lower electrode successively according to epitaxial method by taking the plug as a seed; forming a lower electrode by patterning selected portions of the conductive layer for lower electrode and the glue layer; growing a dielectriclayer and a conductive layer for upper electrode on the lower electrode according to the epitaxial method; and forming an upper electrode by patterning selected portions of the conductive layer for upper layer and the dielectriclayer, wherein the dielectric layer is formed of a layer selected among ferroelectric layer, high dielectric layer or pyroelectric layer.
The present invention further provides a method for fabricating a semiconductor memory device comprising the steps of: forming source and drain regions at selected portions of a semiconductor substrate in which an active region is defined; forming a plug contacted with the source region by growing the semiconductor substrate according to an epitaxial method; forming a gate electrode between the source and the drain regions; forming a first intermetal insulating layer on the semiconductor substrate; forming a bit line contacted with the drain region by penetrating the first intermetal insulating layer; forming a second intermetal insulating layer on the first intermetal insulating layer in which the bit line is formed; polishing the first and the second intermetal insulating layers until a surface of the plug is exposed according to a chemical mechanical polishing process; growing a glue layer and a conductive layer for lower electrode successively according to epitaxial method by taking the plug as a seed; forming a lower electrode by patterning selected portions of the conductive layer for lower electrode and the glue layer; forming a protection layer for surrounding surfaces of the intermetal insulating layers and sidewalls of the glue layer, the lower electrode, the metal oxide type electrode, and simultaneously exposing the surface of the metal oxide type electrode; gro

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