Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-09-24
2003-01-14
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S239000, C438S241000, C438S258000
Reexamination Certificate
active
06506647
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor integrated circuit device and a manufacturing technique therefor. More particularly, the invention relates to the structure of a semiconductor integrated circuit device having DRAM (dynamic random access memory), a logic integrated circuit and the like in combination and also to a technique effective for application to the manufacture thereof.
This invention relates to a semiconductor integrate circuit device and a manufacturing technique therefor. More particularly, the invention relates to the structure of a semiconductor integrated circuit device having DRAM (dynamic random access memory), a logic integrated circuit and the like in combination and also to a technique effective for application to the manufacture thereof.
In order to realize a low resistance of a gate electrode of MISFET, there is known a technique wherein the gate electrode is made of a built-up film of a polysilicon film and a silicide film, or the gate electrode is made of a built-up film of a polysilicon film and a high melting metal such as tungsten or the like (i.e. a so-called polymetal gate).
On the other hand, for a measure of realizing a high-speed operation of a logic integrated circuit unit, there is known a technique wherein MISFET constituting a logic circuit is formed with a silicide film on the surfaces of a source and a drain thereof, respectively.
For instance, in Japanese Laid-open Patent Application No. 2000-091535 corresponding U.S. Pat. No. 6,069,038, a semiconductor integrated circuit device is stated, which makes use, as a gate electrode, of a built-up film of a polysilicon and a silicide film.
Further, in International Laid-open Application WO98/50951 corresponding U.S. patent Ser. No. 09/423,047, there is described a semiconductor integrated circuit device wherein a gate electrode is made of a built-up film of a polysilicon film and a tungsten (W) film and a silicide layer is formed on the surfaces of a source and a drain of MOSFET for a logic circuit.
SUMMARY OF THE INVENTION
We have studied and developed so-called system LSI wherein DRAM and logic LSI are formed in the same semiconductor substrate.
The DRAM formed in the system LSI has MISFET for information transmission and a capacitor element for information storage connected in series. Logic LSI has a logic circuit wherein an n channel-type MISFET and a p channel-type MISFET are appropriately combined.
Accordingly, for the formation of these elements on the same substrate, it is preferred that the MISFET for information transmission in a memory cell-forming region and the n channel-type MISFET and the p channel-type MISFET in a peripheral circuit-forming region where the logic LSI is formed are, respectively, formed according to a common process as far as circumstances permit.
In order to improve the working speed, it is required that the gate electrode of MISFET for information transmission and the gate electrodes and the sources and drains of the n channel-type MISFET and the p channel-type MISFET in the peripheral circuit-forming region be individually low in resistance. For improving the refresh characteristics of DRAM, it is also required that a leakage current between the source and drain of the MISFET for information transmission be very small.
For reducing the resistance of the gate electrode, a polycide structure may be adopted. The term “polycide gate” means a technique of forming a gate electrode by patterning a built-up film of a polysilicon film and a metal silicide film.
However, this technique is disadvantageous in that the concentration of the metal in the metal silicide film cannot be made appreciably high, thus making it difficult to form a gate electrode having a sufficiently low resistance. The reason why the concentration of the metal in the metal silicide film of the polycide gate electrode cannot be made fairly high is as follows. More particularly, after the step of forming the gate electrode, the step of ion implantation for forming source and drain regions and a subsequent thermal treatment step for activating an impurity are necessary, and this, in turn, requires the adoption, as the metal polysilicide film, of a film that has a heat resistance sufficient to withstand the thermal treatment at high temperatures for the activation of the impurity. For instance, when a conductive film having a concentration of a metal higher than a stoichiometric ratio inherent to an alloy layer is formed over a polysilicon film, the metal is diffused through the high-temperature thermal treatment step, with the possibility that the semiconductor substrate is contaminated at the channel region thereof.
In the polycide gate structure, when the metal silicide film is increased in its thickness, the gate electrode can be made low in resistance. Nevertheless, in order to process a thick film, a photoresist film that is proof against the processing is necessary.
Such a thick photoresist film is poor in resolution, so that gate electrodes arranged at small intervals cannot be processed in high precision. Eventually, it becomes difficult to respond to the scale down of LSI.
Where gate electrodes constituted of a thick film are arranged at small intervals, a ratio between the interval and the height of the gate (i.e. an aspect ratio) becomes large, making it difficult to provide an insulating film or the like between the gate electrodes.
To avoid this, studies have been made on a polymetal gate structure for solving the above problem, in which a barrier metal film for preventing the diffusion of a metal and preventing a silicide reaction is interposed between a conductive film having a high metal concentration and a low resistance and a polysilicon film.
This polymetal gate structure includes, in some instance, a gate electrode constituted, for example, of a built-up film of a polysilicon film, a tungsten nitride (WN) film, and a tungsten (W) film. Aside from the tungsten nitride film, other types of metal nitrides and nitride alloys may be appropriately used as the barrier metal film. In addition, materials for use as the conductive film having a high metal concentration and a low resistance may include, aside from tungsten, other types of metals.
As stated hereinabove, for lowering a sheet resistance and a contact resistance of the source and drain regions of MISFET in the peripheral circuit region and reducing the leakage current between the source and drain of MISFET for information transmission, there is known a method wherein a silicide process is applied only to the MISFET in the peripheral circuit-forming region.
This silicide process comprises forming a metal film such as cobalt (Co), titanium (Ti) or the like on a silicon substrate, and thermally treating the film to selectively form a metal silicide layer only in a region where polysilicon or a silicon layer such as of the silicon substrate is exposed.
On the other hand, a thick etching stopper film, which is necessary for a self aligned contact (SAC) process, has to be formed on the gate electrode or side walls of the MISFET for information transmission. The etching stopper film is a film that permits an appropriate selection ratio of etching relative to an interlayer insulating film and includes, for example, an SiN film or the like.
However, where an etching stopper film is formed on the gate electrode of MISFET in the peripheral circuit-forming region along with the formation of the etching stopper film on the gate electrode or side walls of the MISFET for information transmission, it is necessary to remove the etching stopper film from the gate electrode of the MISFET in the peripheral circuit-forming region.
This is for the reason that when contact holes are made over the source and drain regions and the gate electrode of the peripheral circuit region simultaneously, the element isolation region is exposed to etching conditions over a long time, resulting in over-etching. As a result, short-circuiting takes place between a contact plug and the substrate. In order to prevent the short-circuitin
Kuroda Kenichi
Watanabe Kozo
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