Method for fabricating a semiconductor device having a...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S291000, C438S585000

Reexamination Certificate

active

07091093

ABSTRACT:
A gate electrode is formed over a semiconductor region with a gate insulating film interposed therebetween. An extended high-concentration dopant diffused layer of a first conductivity type is formed in part of the semiconductor region beside the gate electrode through diffusion of a first dopant. A pocket dopant diffused layer of a second conductivity type is formed under the extended high-concentration dopant diffused layer through diffusion of heavy ions. The pocket dopant diffused layer includes a segregated part that has been formed through segregation of the heavy ions.

REFERENCES:
patent: 5399506 (1995-03-01), Tsukamoto
patent: 5650340 (1997-07-01), Burr et al.
patent: 5786620 (1998-07-01), Richards et al.
patent: 5923987 (1999-07-01), Burr
patent: 5970353 (1999-10-01), Sultan
patent: 6180443 (2001-01-01), Kang et al.
patent: 6271095 (2001-08-01), Yu
patent: 6319798 (2001-11-01), Yu
patent: 6331458 (2001-12-01), Anjum et al.
patent: 6333217 (2001-12-01), Umimoto et al.
patent: 6391731 (2002-05-01), Chong et al.
patent: 6432802 (2002-08-01), Noda et al.
patent: 6500739 (2002-12-01), Wang et al.
patent: 6548361 (2003-04-01), En et al.
patent: 6720632 (2004-04-01), Noda
patent: 3-272146 (1991-12-01), None
patent: 06-267974 (1994-09-01), None
patent: 11-87706 (1999-03-01), None
G.G. Shahidi et al., Indium Channel Implants for Improved MOSFET Behavior at the 100-nm Channel Length Regime. IEEE 1989, p. 2605.
G.G. Shahidi et al., Indium Channel Implants for Improved Short-Channel Behavior of Submicrometer NMOSFET's. IEEE 1993, pp. 409-411.
P. Bouillon et al., Theoritical Analysis of Kink Effect in C-V Characteristics of Indium-Implnated NMOS Capacitors. IEEE 1998, pp. 19-22.
G.G. Shahidi et al., High-Performance Devices for a 0.15 micron CMOS Technology. IEEE 1993. pp. 466-468.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for fabricating a semiconductor device having a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for fabricating a semiconductor device having a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a semiconductor device having a... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3696823

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.