Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-29
2003-06-03
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S184000, C438S230000, C438S595000, C257S410000
Reexamination Certificate
active
06573132
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including contacts self-aligned with the gate electrode thereof, and also relates to a method for fabricating such a device.
Recently, semiconductor devices of older generations have been replaced with newer ones in at shorter and shorter cycles and the number of miniaturized devices integrated together on a single chip has been steeply rising. Reflecting these tendencies, the size of a contact hole, which is used to interconnect together the gate electrode, diffused layer and interconnection layer of an MOS transistor, has been decreasing. That is to say, the size of a contact, which is formed by filling in the contact hole with a conductive material, has been decreasing year after year. As the design rule has been minimized at such an increasing rate, it has become more and more difficult for the mask overlay accuracy to catch up with such rapid downsizing. Thus, the resultant increase in number of devices integrated is not so striking as the size reduction accomplished.
To ensure much more margin in stacking masks, a technique of forming a contact to be self-aligned with a gate electrode has been vigorously researched and developed these days. In this specification, such a contact will be simply referred to as a “self-aligned contact”. In the prior art, a self-aligned contact is formed in the following manner. First, a gate electrode is covered with a silicon nitride film. Then, an interlevel dielectric film of silicon dioxide, for example, is etched using the silicon nitride film as an etch stopper so as to form a contact hole reaching a diffused layer. Thus, the gate electrode should preferably be completely covered with the silicon nitride film.
FIG. 8
illustrates a cross section of a prior art semiconductor device. As shown in
FIG. 8
, trench isolations
102
are formed on an Si substrate
101
and a transistor is formed in an active region surrounded by the trench isolations
102
. The transistor includes: a gate insulating film
103
of silicon dioxide; a polysilicon gate electrode
104
; an insulator cap
105
of silicon nitride; a pad oxide film
106
of silicon dioxide; and a nitride sidewall
107
. As shown in
FIG. 8
, the gate electrode
104
is formed on the gate insulating film
103
and the insulator cap
105
is formed on the gate electrode
104
. And the pad oxide film
106
covers the side faces of the gate electrode
104
and a part of the upper surface of the substrate
101
. The nitride sidewall
107
covers the respective side faces of the gate electrode
104
and the insulator cap
105
. The transistor further includes LDD regions
110
and heavily doped source/drain regions
111
, both of which regions defined within the Si substrate
101
. And a contact
109
is provided to pass through an interlevel dielectric film
108
formed on the substrate
101
and to reach one of the heavily doped source/drain regions
111
. Depending on the direction of mask stacking error, the contact
109
comes into partial contact with the insulator cap
105
and the nitride sidewall
107
to serve as a self-aligned contact.
The semiconductor device may be fabricated in the following manner. First, silicon dioxide, polysilicon and silicon nitride films are deposited in this order on a semiconductor substrate
101
in which wells (not shown) are defined. Next, the silicon nitride and polysilicon films are patterned by photolithography and dry etching techniques, thereby forming the insulator cap
105
and gate electrode
104
. In this process step, the silicon dioxide film is usually patterned into the same shape to form the gate insulating film
103
. Then, heat treatment is conducted within oxygen ambient, thereby forming the pad oxide film
106
of silicon dioxide to cover the side faces of the gate electrode
104
and a part of the upper surface of the Si substrate
101
. Thereafter, a silicon nitride film is deposited over the entire surface of the substrate and then etched back, thereby forming the sidewall
107
of silicon nitride over the respective side faces of the insulator cap
105
and the gate electrode
104
. Subsequently, the interlevel dielectric film
108
is formed and the contact
109
is formed as an extension from the heavily doped source/drain regions
111
.
In this structure, the polysilicon gate electrode
104
is covered with the silicon nitride insulator cap
105
and the nitride sidewall
107
. Accordingly, if dry etching is performed using the silicon nitride film as an etch stopper to open the contact hole, then a self-aligned contact can be formed.
As can be seen, according to the conventional method for fabricating the semiconductor device, the pad oxide film
106
is formed as a thermal oxide film before the nitride sidewall
107
is formed. Without this pad oxide film
106
, the nitride sidewall
107
would be in direct contact with the Si substrate
101
. In such a situation, stress is applied through the nitride film to the gate insulating film
103
, thus deteriorating the quality of the gate insulating film
103
. In addition, since the transistors formed this way cannot recover from damage caused by a sintering process, the characteristics of resultant transistors are non-uniform. For these reasons, the pad oxide film
106
is required to prevent the nitride sidewall
107
from coming into direct contact with the Si substrate
101
.
As semiconductor devices have been downsized and the number of those devices integrated has been increasing, it has become more and more necessary to reduce the resistance of the date electrode thereof. For that purpose, a gate electrode for an MOS transistor with the single-layer polysilicon film shown in
FIG. 8
is no longer preferred. Instead, a socalled “polycide” or “poly-metal” structure prevails these days. Specifically, in a recent gate electrode structure, a single-layer metal or metal compound (such as metal silicide or nitride) film or a multilayer structure thereof is deposited on a polysilicon film.
However, many of these metals or metal compounds like metal silicides or nitrides are poorly resistant to oxidation. Accordingly, the process step of forming the pad oxide film
106
such as that shown in
FIG. 8
by thermal oxidation is not applicable to a semiconductor device including the polycide or poly-metal gate electrode.
An alternative method has also been proposed to prevent a silicon nitride film from coming into direct contact with a semiconductor substrate. According to the technique, a silicon dioxide film is deposited by a CVD process, for example, instead of forming a pad oxide film by thermal oxidation.
FIG. 9
illustrates a cross section of a semiconductor device formed by such a method. As shown in
FIG. 9
, an upper gate electrode
104
b
made of a refractory metal (or a silicide thereof) is formed on a lower gate electrode
104
a
of polysilicon. A CVD pad oxide film
115
with an L cross section is formed to cover the respective side faces of the insulator cap
105
land the upper and lower gate electrodes
104
b
and
104
a
and part of the surface of the Si substrate
101
. And the nitride sidewall
107
is formed on the CVD pad oxide film
115
. The other members of the device are the same as those illustrated in FIG.
8
.
In the structure shown in
FIG. 9
, however, when a contact hole is formed to pass through the interlevel dielectric film
108
, an upper edge of the nitride sidewall
107
might be etched away unintentionally as in a region Ret shown in FIG.
9
. The reason is believed to be as follows. According to this method, when the nitride sidewall
107
and the insulator cap
105
are exposed inside the contact hole, the upper edge of the CVD pad oxide film
115
is also exposed there. Thus, if the upper edge of the CVD pad oxide film
115
is etched, then the nitride sidewall
107
is etched from both sides, thus adversely decreasing the etch selectivity between the interlevel dielectric film of silicon dioxide and the silicon nitride film.
SUMMARY OF THE INVENTION
An objec
Kanazawa Masato
Uehara Takashi
Chaudhuri Olik
Matsushita Electric - Industrial Co., Ltd.
Nixon & Peabody LLP
Studebaker Donald R.
Toledo Fernando
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