Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-12-26
2004-05-11
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S212000, C438S245000, C438S259000
Reexamination Certificate
active
06734058
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a semiconductor device having a cylinder type transistor.
2. Description of the Prior Art
As generally known in the art, a transistor, in particular, an MOS transistor generally belongs to a category of insulated gate field effect transistors (FET) and uses electrons induced on the surface of a silicon substrate opposing a metal (typically polysilicon) gate material in the structure of an MOS (metal oxide semiconductor) capacitor as electrical currents. In such a case, when the carrier is an electron, it is called an N-channel, and when the carrier is a hole, it is called a P-channel.
The MOS transistor is essentially a majority carrier device, and it has a good characteristic as regards its high frequency activation and has advantages in that driving is easy and the circuit design can be simplified due to the electrical insulation of a gate by an insulating layer such as a gate oxide layer.
According to a method for fabricating a transistor in a process for making a semiconductor device in accordance with a conventional art, as shown in
FIG. 1
, a gate oxide layer
3
is formed on a semiconductor device wherein a field oxide layer has been formed, and a gate electrode
4
is formed on a desired part of the gate oxide layer
3
.
Then, low concentration impurities are implanted into the semiconductor substrate by using the gate electrode
4
as an ion implantation mask, thereby forming a low concentration impurity region
5
. Next, a spacer is formed so that an insulating layer remains at both sides of the gate electrode
4
, by a blanket etching process.
Subsequently, a source/drain region is formed by implanting high concentration impurity into the exposed substrate with using the gate electrode
4
and the spacer
6
as ion implantation masks thereby accomplishing the transistor.
However, according to the fabricating method for a semiconductor device in accordance with the conventional art, several problems occur as follows.
According to the conventional art, production costs have been increased, because the fabricating process of the transistor has become complicated with the increase of the degree of integration. Also, as regards the semiconductor device, junction capacitance and junction leakage currents have been increased, and it has been difficult to isolate the semiconductor devices.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a method for fabricating a highly integrated semiconductor device wherein a vertical cylinder type transistor has been formed inside of an epitaxial silicon layer of a cylinder type.
In order to accomplish this object, there is provided a method for fabricating a semiconductor device, comprising the steps of: forming an insulating layer and a nitride layer sequentially on a semiconductor substrate; selectively removing the insulating layer and the nitride layer, resulting in the formation of a first contact hole; forming a silicon layer in the first contact hole after the removal of a part of the insulating layer at the side walls of the first contact hole; forming a trench through selective removal of the silicon layer; forming a source region in the semiconductor substrate and a drain region on an upper part of the trench, after the removal of the nitride layer; forming a gate oxide layer and gates sequentially at the side walls of the trench; forming a planarization layer on the resultant structure to fill the trench; forming a second contact hole that exposes the gate, the drain region, and the source region through selective patterning the resultant structure; and forming plugs in the exposed second contact hole.
REFERENCES:
patent: 5291438 (1994-03-01), Witek et al.
patent: 5382816 (1995-01-01), Mitsui
patent: 5547889 (1996-08-01), Kim
patent: 5872037 (1999-02-01), Iwamatsu et al.
patent: 6075265 (2000-06-01), Goebel et al.
patent: 6197641 (2001-03-01), Hergenrother et al.
Dongbu Electronics Co. Ltd.
Keefer Timothy J.
Perkins Pamela E
Wildman Harrold Allen & Dixon LLP
Zarabian Amir
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