Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-04-15
2003-08-05
Nguyen, Viet Q. (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S381000
Reexamination Certificate
active
06602748
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 2000-156773 filed May 26, 2000, the contents thereof being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device fabricating method and, more particularly, to a semiconductor device fabricating method for forming an insulation film on an entire main surface of a substrate for the device, including an uneven, patterned surface portion of the main surface.
2. Discussion of the Related Art
With reference to
FIGS. 1A through 8
, sequential steps of a method of fabricating a DRAM/logic hybrid type semiconductor device of the related art (in the following explanation, a DRAM/logic hybrid type semiconductor device will be termed merely as a “hybrid type semiconductor device” or a “DRAM & logic device”) are explained and the problem mentioned above, of forming a film on an uneven, patterned surface, is explained from a practical standpoint.
FIGS. 1A and 1B
are cross-sectional views of structures produced at successive steps a and b, respectively, in the course of fabricating a hybrid type semiconductor device in accordance with a method of the related art. In step a and as shown in
FIG. 1A
, n-type wells
5
and
6
are formed within active regions
3
and
4
, respectively, defined within an element isolating insulation film
2
on a major surface of a silicon substrate
1
, the p-type well
7
being formed within the n-type well
6
. Moreover, gate electrodes
10
,
11
,
12
and
13
of corresponding MOS transistors are formed within respective active regions
3
and
4
of the common silicon substrate
1
by sequentially laminating thereon a polysilicon film (
10
a
,
11
a
,
12
a
and
13
a
), a tungsten silicide film (
10
b
,
11
b
,
12
b
and
13
b
) and a silicon nitride film (
10
c
,
11
c
,
12
c
and
13
c
) and then patterning same. Respective source/drain regions
15
and
16
of respective MOS transistors in the active regions
4
and
3
are formed to a shallow depth within the corresponding n-type and p-type wells
6
and
7
. On the left and right side of the drawings, relatively to the center, there are schematically illustrated a DRAM part active region
3
and a logic device part active region
4
, respectively.
Next, in step b and as shown in
FIG. 1B
, a silicon nitride film
20
is formed so as to cover the entire surface of the DRAM part active region
3
(left side of figure) and the logic device part active region
4
(right side of
FIG. 1B
) including the surfaces of gate electrodes
10
,
11
,
12
,
13
. The DRAM part active region
3
subsequently is covered with a resist (not shown). The logic active part
4
(right side of
FIGS. 1A and 1B
) is not covered with the resist and instead is exposed. The silicon nitride film
20
is removed, through an etch-back step using a dry etching process, and a residue thereof designated at
25
on the side surfaces of the gate electrode
10
of the Logic device part
4
is used as a side wall spacer. Thereafter, using the remaining resist, ion implantation is performed for producing diffused source/drain regions
26
in the substrate surface of the Logic device part
4
(right side of FIGS.
1
A and
1
B). Lastly, the resist used as the mask is removed to provide the structure illustrated in FIG.
1
B.
Subsequently, in step c and as shown in
FIG. 2A
, a cobalt silicide (CoSi) film
30
is formed, using a self-alignment method, selectively on the surface of the source/drain region
15
of the Logic device part
4
. Thereafter, a silicon nitride film
33
, that is used as a stopper for opening of contact windows, as a post-process, is formed by deposition on the entire surface of the substrate
1
, to provide the structure illustrated in FIG.
2
A.
In step d and as shown in
FIG. 2B
, when a BPSG film
35
is formed on the silicon nitride film
33
by a CVD (chemical vapor deposition) method, voids
34
tend to be generated therein, in the portions following the gaps between adjacent gate electrodes
11
and
12
and
12
and
13
, because the gate electrode interval (i.e., the spacing between adjacent gates) is small, like a slit, in the DRAM part
3
(left side in the figure).
Subsequently, in step e and as shown in
FIG. 3A
, the voids
34
are eliminated through reflow annealing of the BPSG film
35
. The BPSG film
35
is known to have a merit that it will easily reflow at a comparatively low temperature; however, annealing at 800° C. or higher is required to definitely eliminate the voids
34
. This temperature will be explained in more detail when explaining the problem of this process.
Next, in step f as shown in
FIG. 3B
, contact holes
36
,
37
are opened in the BPSG film
35
by a dry etching method in such a manner so as to reach the regions
16
of DRAM device active region
3
of the substrate
1
; further, respective contact electrodes
40
,
41
, consisting of conductive material, are formed within these contact holes
36
,
37
.
Moreover, in step g and as shown in
FIG. 4
, a silicon oxide (SiO
2
) film
45
, of a constant, or uniform, thickness, is formed on the entire surface of film
35
and a film
46
is then formed on film
45
by sequentially laminating titanium and titanium nitride layers thereon. Bit lines
47
are then formed, extending through respective patterned openings, or windows,
45
′ for electrical connection with the (polysilicon) contact electrodes
40
,
41
which extend through respective openings
36
and
37
in the BPSG film
35
.
Moreover, in step h, as shown in
FIG. 5
, a silicon nitride film
49
is deposited on the entire surface of the substrate
1
, including the surface of the bit line
47
and film
45
. Next, a plasma oxide film
48
is deposited on the bit line
47
by a plasma CVD (chemical vapor deposition) method; the plasma CVD step, however, cuts, or abrads, the silicon nitride film
49
by a sputtering effect of argon gas, and thereby titanium is exposed to the plasma during the plasma CVD process. Accordingly, the exposed surface of titanium is oxidized and titanium oxide
44
is formed, as illustrated in FIG.
5
. Subsequently, a further plasma oxide film
48
is deposited so as to cover the entire surface.
Subsequently, in step i and as shown in
FIG. 6
, a deep contact window
48
′ is opened in the plasma oxide film
48
, using a dry etching method, to expose the surface of the contact electrode
41
, which is not connected with the bit line
47
; further, an amorphous silicon plug
50
is formed so as to fill the contact window
48
′.
Next, in step j and as illustrated in
FIG. 7
, a memory cell capacitor is formed in connection with the amorphous silicon plug
50
. In this process, a conductive layer is formed on the entire surface of the plasma oxide film
48
and is then patterned to form the storage electrode
51
; thereafter, a dielectric material layer is formed on the entire surface, including that of the storage electrode
51
, which is then patterned to form the storage layer
52
and a storage electrode layer then is formed on the entire surface and patterned to form an opposing electrode
53
, thereby to complete the memory cell capacitor structure. Subsequently, a sufficiently thick plasma oxide silicon film
58
is formed on the entire surface, including that of the memory cell capacitor structure. Thereby, the structure of
FIG. 7
is completed.
Next, a metal multilayer-wiring layer forming process is performed, in step k illustrated in
FIG. 8. A
deep contact window
60
is opened, extending from the surface of the plasma oxide silicon film
58
, deposited in the preceding process step j, to the logic device part
4
(right side of the figure). The contact window
60
can be opened by a well-known method combining dry etching with photolithography. After the opening process, a thin barrier metal layer
61
is deposited on the internal bottom and sidewall surfaces of window
60
in such a manner so as
Nguyen Viet Q.
Nhu David
Staas & Halsey , LLP
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